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Commit 8f23926d authored by Taniya Das's avatar Taniya Das
Browse files

clk: qcom: clk-alpha-pll: Add support for Agera PLL 



Agera PLL is required to be supported from HLOS clock controller, thus
add support for agera pll ops.

Change-Id: I77b2a741667accf9bd0eecfcd0dabfaf7596345f
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent 78e4312f

drivers/clk/qcom/clk-alpha-pll.c

+113 −0
Original line number Diff line number Diff line
@@ -192,6 +192,16 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { 
		[PLL_OFF_OPMODE] = 0x28,

		[PLL_OFF_STATUS] = 0x38,

	},

	[CLK_ALPHA_PLL_TYPE_AGERA] =  {

		[PLL_OFF_L_VAL] = 0x04,

		[PLL_OFF_ALPHA_VAL] = 0x08,

		[PLL_OFF_USER_CTL] = 0x0c,

		[PLL_OFF_CONFIG_CTL] = 0x10,

		[PLL_OFF_CONFIG_CTL_U] = 0x14,

		[PLL_OFF_TEST_CTL] = 0x18,

		[PLL_OFF_TEST_CTL_U] = 0x1c,

		[PLL_OFF_STATUS] = 0x2c,

	},

};

EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
@@ -3476,3 +3486,106 @@ const struct clk_ops clk_regera_pll_ops = { 
#endif

};

EXPORT_SYMBOL_GPL(clk_regera_pll_ops);



int clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,

					const struct alpha_pll_config *config)

{

	u32 val, mask;



	if (!config) {

		pr_err("PLL configuration missing.\n");

		return -EINVAL;

	}



	if (config->l)

		regmap_write(regmap, PLL_L_VAL(pll), config->l);



	if (config->alpha)

		regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);



	if (config->config_ctl_val)

		regmap_write(regmap, PLL_CONFIG_CTL(pll),

						config->config_ctl_val);



	if (config->config_ctl_hi_val)

		regmap_write(regmap, PLL_CONFIG_CTL_U(pll),

						config->config_ctl_hi_val);



	val = config->main_output_mask;

	val |= config->aux_output_mask;

	val |= config->aux2_output_mask;

	val |= config->early_output_mask;



	mask = config->main_output_mask;

	mask |= config->aux_output_mask;

	mask |= config->aux2_output_mask;

	mask |= config->early_output_mask;



	regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);



	if (config->post_div_mask) {

		mask = config->post_div_mask;

		val = config->post_div_val;

		regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);

	}



	if (config->test_ctl_val)

		regmap_write(regmap, PLL_TEST_CTL(pll),

						config->test_ctl_val);



	if (config->test_ctl_hi_val)

		regmap_write(regmap,  PLL_TEST_CTL_U(pll),

						config->test_ctl_hi_val);

	return 0;

}

EXPORT_SYMBOL(clk_agera_pll_configure);



static int alpha_pll_agera_set_rate(struct clk_hw *hw, unsigned long rate,

							unsigned long prate)

{

	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);

	u32 l, alpha_width = pll_alpha_width(pll);

	unsigned long rrate;

	u64 a;



	rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);



	/*

	 * Due to limited number of bits for fractional rate

	 * programming, the rounded up rate could be marginally

	 * higher than the requested rate.

	 */

	if (rrate > (rate + PLL_OUT_RATE_MARGIN) || rrate < rate) {

		pr_err("Call set rate on the PLL with rounded rates!\n");

		return -EINVAL;

	}



	/* change L_VAL without having to go through the power on sequence */

	regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);

	regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);



	/* Ensure that the write above goes through before proceeding. */

	mb();



	if (clk_hw_is_enabled(hw))

		return wait_for_pll_enable_lock(pll);



	return 0;

}



const struct clk_ops clk_agera_pll_ops = {

	.prepare = clk_prepare_regmap,

	.unprepare = clk_unprepare_regmap,

	.pre_rate_change = clk_pre_change_regmap,

	.post_rate_change = clk_post_change_regmap,

	.enable = clk_alpha_pll_enable,

	.disable = clk_alpha_pll_disable,

	.is_enabled = clk_alpha_pll_is_enabled,

	.recalc_rate = clk_alpha_pll_recalc_rate,

	.round_rate = clk_alpha_pll_round_rate,

	.set_rate = alpha_pll_agera_set_rate,

#ifdef CONFIG_COMMON_CLK_QCOM_DEBUG

	.list_rate_vdd_level = clk_list_rate_vdd_level,

#endif

};

EXPORT_SYMBOL(clk_agera_pll_ops);

drivers/clk/qcom/clk-alpha-pll.h

+4 −0
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@ enum { 
	CLK_ALPHA_PLL_TYPE_LUCID_5LPE,

	CLK_ALPHA_PLL_TYPE_ZONDA_5LPE,

	CLK_ALPHA_PLL_TYPE_REGERA,

	CLK_ALPHA_PLL_TYPE_AGERA,

	CLK_ALPHA_PLL_TYPE_MAX,

};
@@ -156,6 +157,7 @@ extern const struct clk_ops clk_trion_pll_postdiv_ops; 
extern const struct clk_ops clk_trion_pll_ops;



extern const struct clk_ops clk_regera_pll_ops;

extern const struct clk_ops clk_agera_pll_ops;



void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,

			     const struct alpha_pll_config *config);
@@ -175,4 +177,6 @@ int clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 
				const struct alpha_pll_config *config);

int clk_regera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,

				const struct alpha_pll_config *config);

int clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,

					const struct alpha_pll_config *config);

#endif