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Commit 8f13b607 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-next-4.19' of git://people.freedesktop.org/~agd5f/linux into drm-next 



Fixes for 4.19:
- Fix build when KCOV is enabled
- Misc display fixes
- A couple of SR-IOV fixes
- Fence fixes for eviction handling for KFD
- Misc other fixes

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180822203813.2733-1-alexander.deucher@amd.com
parents 4d1608ee 9d1d02ff

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

+46 −57
Original line number Diff line number Diff line
@@ -206,11 +206,9 @@ static int amdgpu_amdkfd_remove_eviction_fence(struct amdgpu_bo *bo, 
					struct amdgpu_amdkfd_fence ***ef_list,

					unsigned int *ef_count)

{

	struct reservation_object_list *fobj;

	struct reservation_object *resv;

	unsigned int i = 0, j = 0, k = 0, shared_count;

	unsigned int count = 0;

	struct amdgpu_amdkfd_fence **fence_list;

	struct reservation_object *resv = bo->tbo.resv;

	struct reservation_object_list *old, *new;

	unsigned int i, j, k;



	if (!ef && !ef_list)

		return -EINVAL;
@@ -220,76 +218,67 @@ static int amdgpu_amdkfd_remove_eviction_fence(struct amdgpu_bo *bo, 
		*ef_count = 0;

	}



	resv = bo->tbo.resv;

	fobj = reservation_object_get_list(resv);



	if (!fobj)

	old = reservation_object_get_list(resv);

	if (!old)

		return 0;



	preempt_disable();

	write_seqcount_begin(&resv->seq);

	new = kmalloc(offsetof(typeof(*new), shared[old->shared_max]),

		      GFP_KERNEL);

	if (!new)

		return -ENOMEM;



	/* Go through all the shared fences in the resevation object. If

	 * ef is specified and it exists in the list, remove it and reduce the

	 * count. If ef is not specified, then get the count of eviction fences

	 * present.

	/* Go through all the shared fences in the resevation object and sort

	 * the interesting ones to the end of the list.

	 */

	shared_count = fobj->shared_count;

	for (i = 0; i < shared_count; ++i) {

	for (i = 0, j = old->shared_count, k = 0; i < old->shared_count; ++i) {

		struct dma_fence *f;



		f = rcu_dereference_protected(fobj->shared[i],

		f = rcu_dereference_protected(old->shared[i],

					      reservation_object_held(resv));



		if (ef) {

			if (f->context == ef->base.context) {

				dma_fence_put(f);

				fobj->shared_count--;

			} else {

				RCU_INIT_POINTER(fobj->shared[j++], f);

			}

		} else if (to_amdgpu_amdkfd_fence(f))

			count++;

		if ((ef && f->context == ef->base.context) ||

		    (!ef && to_amdgpu_amdkfd_fence(f)))

			RCU_INIT_POINTER(new->shared[--j], f);

		else

			RCU_INIT_POINTER(new->shared[k++], f);

	}

	write_seqcount_end(&resv->seq);

	preempt_enable();

	new->shared_max = old->shared_max;

	new->shared_count = k;



	if (ef || !count)

		return 0;

	if (!ef) {

		unsigned int count = old->shared_count - j;



	/* Alloc memory for count number of eviction fence pointers. Fill the

	 * ef_list array and ef_count

		/* Alloc memory for count number of eviction fence pointers.

		 * Fill the ef_list array and ef_count

		 */

	fence_list = kcalloc(count, sizeof(struct amdgpu_amdkfd_fence *),

			     GFP_KERNEL);

	if (!fence_list)

		*ef_list = kcalloc(count, sizeof(**ef_list), GFP_KERNEL);

		*ef_count = count;



		if (!*ef_list) {

			kfree(new);

			return -ENOMEM;

		}

	}



	/* Install the new fence list, seqcount provides the barriers */

	preempt_disable();

	write_seqcount_begin(&resv->seq);

	RCU_INIT_POINTER(resv->fence, new);

	write_seqcount_end(&resv->seq);

	preempt_enable();



	j = 0;

	for (i = 0; i < shared_count; ++i) {

	/* Drop the references to the removed fences or move them to ef_list */

	for (i = j, k = 0; i < old->shared_count; ++i) {

		struct dma_fence *f;

		struct amdgpu_amdkfd_fence *efence;



		f = rcu_dereference_protected(fobj->shared[i],

		f = rcu_dereference_protected(new->shared[i],

					      reservation_object_held(resv));



		efence = to_amdgpu_amdkfd_fence(f);

		if (efence) {

			fence_list[k++] = efence;

			fobj->shared_count--;

		} else {

			RCU_INIT_POINTER(fobj->shared[j++], f);

		}

		if (!ef)

			(*ef_list)[k++] = to_amdgpu_amdkfd_fence(f);

		else

			dma_fence_put(f);

	}



	write_seqcount_end(&resv->seq);

	preempt_enable();



	*ef_list = fence_list;

	*ef_count = k;

	kfree_rcu(old, rcu);



	return 0;

}

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+1 −1
Original line number Diff line number Diff line
@@ -2274,7 +2274,7 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type) 
	case CHIP_VEGA10:

	case CHIP_VEGA12:

	case CHIP_VEGA20:

#ifdef CONFIG_X86

#if defined(CONFIG_DRM_AMD_DC_DCN1_0)

	case CHIP_RAVEN:

#endif

		return amdgpu_dc != 0;

drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c

+6 −15
Original line number Diff line number Diff line
@@ -53,9 +53,8 @@ static int amdgpu_sched_process_priority_override(struct amdgpu_device *adev, 
						  int fd,

						  enum drm_sched_priority priority)

{

	struct file *filp = fcheck(fd);

	struct file *filp = fget(fd);

	struct drm_file *file;

	struct pid *pid;

	struct amdgpu_fpriv *fpriv;

	struct amdgpu_ctx *ctx;

	uint32_t id;
@@ -63,20 +62,12 @@ static int amdgpu_sched_process_priority_override(struct amdgpu_device *adev, 
	if (!filp)

		return -EINVAL;



	pid = get_pid(((struct drm_file *)filp->private_data)->pid);



	mutex_lock(&adev->ddev->filelist_mutex);

	list_for_each_entry(file, &adev->ddev->filelist, lhead) {

		if (file->pid != pid)

			continue;



	file = filp->private_data;

	fpriv = file->driver_priv;

	idr_for_each_entry(&fpriv->ctx_mgr.ctx_handles, ctx, id)

		amdgpu_ctx_priority_override(ctx, priority);

	}

	mutex_unlock(&adev->ddev->filelist_mutex);



	put_pid(pid);

	fput(filp);



	return 0;

}

drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c

+3 −0
Original line number Diff line number Diff line
@@ -38,6 +38,7 @@ int vega20_reg_base_init(struct amdgpu_device *adev) 
		adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));

		adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));

		adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));

		adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));

		adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i]));

		adev->reg_offset[VCE_HWIP][i] = (uint32_t *)(&(VCE_BASE.instance[i]));

		adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));
@@ -46,6 +47,8 @@ int vega20_reg_base_init(struct amdgpu_device *adev) 
		adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i]));

		adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(SDMA1_BASE.instance[i]));

		adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));

		adev->reg_offset[NBIF_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));

		adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));

	}

	return 0;

}

drivers/gpu/drm/amd/amdgpu/vi.c

+2 −2
Original line number Diff line number Diff line
@@ -112,8 +112,8 @@ static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg) 
	u32 r;



	spin_lock_irqsave(&adev->smc_idx_lock, flags);

	WREG32(mmSMC_IND_INDEX_11, (reg));

	r = RREG32(mmSMC_IND_DATA_11);

	WREG32_NO_KIQ(mmSMC_IND_INDEX_11, (reg));

	r = RREG32_NO_KIQ(mmSMC_IND_DATA_11);

	spin_unlock_irqrestore(&adev->smc_idx_lock, flags);

	return r;

}