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Commit 8f076761 authored by Andrea Venturi's avatar Andrea Venturi Committed by Maxime Ripard
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clk: sunxi: mod1 clock should modify it's parent 



add CLK_SET_RATE_PARENT to modify the rate on clk upstream

Signed-off-by: default avatarMarcus Cooper <codekipper@gmail.com>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
parent 92a39d90

drivers/clk/sunxi/clk-a10-mod1.c

+1 −1
Original line number Diff line number Diff line
@@ -62,7 +62,7 @@ static void __init sun4i_mod1_clk_setup(struct device_node *node) 
	clk = clk_register_composite(NULL, clk_name, parents, i,

				     &mux->hw, &clk_mux_ops,

				     NULL, NULL,

				     &gate->hw, &clk_gate_ops, 0);

				     &gate->hw, &clk_gate_ops, CLK_SET_RATE_PARENT);

	if (IS_ERR(clk))

		goto err_free_gate;