Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 8f06f5d3 authored by Jianqun's avatar Jianqun Committed by Heiko Stuebner
Browse files

clk: rockchip: rk3288: removing the CLK_SET_RATE_PARENT from i2s_clkout 



Removing the CLK_SET_RATE_PARENT from i2s_clkout, to limit i2s0_clkout
to select between its two parent without being able influence the core
i2s clock.

Tested on rk3288 board, suggested by Heiko.

Signed-off-by: default avatarJianqun <jay.xu@rock-chips.com>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent cd9b4609

drivers/clk/rockchip/clk-rk3288.c

+1 −1
Original line number Diff line number Diff line
@@ -307,7 +307,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { 
			RK3288_CLKGATE_CON(4), 2, GFLAGS),

	MUX(0, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT,

			RK3288_CLKSEL_CON(4), 8, 2, MFLAGS),

	COMPOSITE_NODIV(0, "i2s0_clkout", mux_i2s_clkout_p, CLK_SET_RATE_PARENT,

	COMPOSITE_NODIV(0, "i2s0_clkout", mux_i2s_clkout_p, 0,

			RK3288_CLKSEL_CON(4), 12, 1, MFLAGS,

			RK3288_CLKGATE_CON(4), 0, GFLAGS),

	GATE(SCLK_I2S0, "sclk_i2s0", "i2s_pre", CLK_SET_RATE_PARENT,