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Commit 8ea59e67 authored by Vandita Kulkarni's avatar Vandita Kulkarni Committed by Rodrigo Vivi
Browse files

drm/i915/icl: Use helper functions to classify the ports 



Use intel_port_is_tc and intel_port_is_combophy
functions to replace the individual port checks
from port C to F and port A to B respectively.

Signed-off-by: default avatarVandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: default avatarMahesh Kumar <mahesh1.kumar@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Madhav Chauhan <madhav.chauhan@intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181003072203.12848-5-mahesh1.kumar@intel.com
parent cb6caf7e

drivers/gpu/drm/i915/intel_display.c

+4 −11
Original line number Diff line number Diff line
@@ -9269,24 +9269,17 @@ static void icelake_get_ddi_pll(struct drm_i915_private *dev_priv, 
	u32 temp;



	/* TODO: TBT pll not implemented. */

	switch (port) {

	case PORT_A:

	case PORT_B:

	if (intel_port_is_combophy(dev_priv, port)) {

		temp = I915_READ(DPCLKA_CFGCR0_ICL) &

		       DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);

		id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);



		if (WARN_ON(id != DPLL_ID_ICL_DPLL0 && id != DPLL_ID_ICL_DPLL1))

			return;

		break;

	case PORT_C:

	case PORT_D:

	case PORT_E:

	case PORT_F:

	} else if (intel_port_is_tc(dev_priv, port)) {

		id = icl_port_to_mg_pll_id(port);

		break;

	default:

		MISSING_CASE(port);

	} else {

		WARN(1, "Invalid port %x\n", port);

		return;

	}

drivers/gpu/drm/i915/intel_dpll_mgr.c

+4 −10
Original line number Diff line number Diff line
@@ -2867,6 +2867,7 @@ static struct intel_shared_dpll * 
icl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,

	     struct intel_encoder *encoder)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	struct intel_digital_port *intel_dig_port =

			enc_to_dig_port(&encoder->base);

	struct intel_shared_dpll *pll;
@@ -2876,18 +2877,12 @@ icl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state, 
	int clock = crtc_state->port_clock;

	bool ret;



	switch (port) {

	case PORT_A:

	case PORT_B:

	if (intel_port_is_combophy(dev_priv, port)) {

		min = DPLL_ID_ICL_DPLL0;

		max = DPLL_ID_ICL_DPLL1;

		ret = icl_calc_dpll_state(crtc_state, encoder, clock,

					  &pll_state);

		break;

	case PORT_C:

	case PORT_D:

	case PORT_E:

	case PORT_F:

	} else if (intel_port_is_tc(dev_priv, port)) {

		if (intel_dig_port->tc_type == TC_PORT_TBT) {

			min = DPLL_ID_ICL_TBTPLL;

			max = min;
@@ -2899,8 +2894,7 @@ icl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state, 
			ret = icl_calc_mg_pll_state(crtc_state, encoder, clock,

						    &pll_state);

		}

		break;

	default:

	} else {

		MISSING_CASE(port);

		return NULL;

	}