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Commit 8e71903a authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "arm64: defconfig: Enable clock controllers for SM6150"

parents 503b958a f4186977
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+7 −0
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@@ -27,3 +27,10 @@ CONFIG_PHY_QCOM_UFS=m
CONFIG_PHY_QCOM_UFS_V3=m
CONFIG_SCSI_UFS_QCOM=m
CONFIG_SCSI_UFS_BSG=y
CONFIG_SM_CAMCC_6150=m
CONFIG_SM_DISPCC_6150=m
CONFIG_SM_GPUCC_6150=m
CONFIG_SM_VIDEOCC_6150=m
CONFIG_SM_SCC_6150=m
CONFIG_MSM_CLK_AOP_QMP=m
CONFIG_ARM_QCOM_CPUFREQ_HW=m
+1 −0
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@@ -20,3 +20,4 @@ CONFIG_INTERCONNECT_TEST=y
CONFIG_SCSI_UFSHCD_QTI=y
CONFIG_SCSI_UFS_BSG=y
CONFIG_SCSI_UFSHCD=y
CONFIG_SM_DEBUGCC_6150=y
+28 −0
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@@ -719,6 +719,34 @@ config SM_GPUCC_6150
	  Say Y if you want to support graphics controller devices and
	  functionality such as 3D graphics.

config SM_VIDEOCC_6150
	tristate "SM6150 Video Clock Controller"
	select SM_GCC_6150
	help
	  Support for the video clock controller on Qualcomm Technologies, Inc.
	  SM6150 devices.
	  Say Y if you want to support video devices and functionality such as
	  video encode/decode.

config SM_SCC_6150
	tristate "SM6150 Sensor Clock Controller"
	select SM_GCC_6150
	help
	  Support for the sensor clock controller on Qualcomm Technologies, Inc.
	  SM6150 devices.  The sensor controller contains several QUP clocks
	  which can be managed using DFS.  This controller is typically owned by
	  the sensor processor.  However, on some systems it is instead owned
	  by the application processor.

config SM_DEBUGCC_6150
	tristate "SM6150 Debug Clock Controller"
	depends on COMMON_CLK_QCOM
	help
	  Support for the debug clock controller on Qualcomm Technologies, Inc
	  SM6150 devices.
	  Say Y if you want to support the debug clocks such as
	  clock measurement functionality.

endif

config VIRTIO_CLK
+3 −0
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@@ -75,6 +75,7 @@ obj-$(CONFIG_SM_CAMCC_6150) += camcc-sm6150.o
obj-$(CONFIG_SM_CAMCC_8150) += camcc-sm8150.o
obj-$(CONFIG_SM_CAMCC_SHIMA) += camcc-shima.o
obj-$(CONFIG_SM_CAMCC_YUPIK) += camcc-yupik.o
obj-$(CONFIG_SM_DEBUGCC_6150) += debugcc-sm6150.o
obj-$(CONFIG_SM_DEBUGCC_8150) += debugcc-sm8150.o
obj-$(CONFIG_SM_DEBUGCC_HOLI) += debugcc-holi.o
obj-$(CONFIG_SM_DEBUGCC_SHIMA) += debugcc-shima.o
@@ -95,7 +96,9 @@ obj-$(CONFIG_SM_GPUCC_HOLI) += gpucc-holi.o
obj-$(CONFIG_SM_GPUCC_SHIMA) += gpucc-shima.o
obj-$(CONFIG_SM_GPUCC_YUPIK) += gpucc-yupik.o
obj-$(CONFIG_SM_NPUCC_8150) += npucc-sm8150.o
obj-$(CONFIG_SM_SCC_6150) += scc-sm6150.o
obj-$(CONFIG_SM_SCC_8150) += scc-sm8150.o
obj-$(CONFIG_SM_VIDEOCC_6150) += videocc-sm6150.o
obj-$(CONFIG_SM_VIDEOCC_8150) += videocc-sm8150.o
obj-$(CONFIG_SM_VIDEOCC_SHIMA) += videocc-shima.o
obj-$(CONFIG_SM_VIDEOCC_YUPIK) += videocc-yupik.o
+1 −0
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@@ -4458,3 +4458,4 @@ const struct clk_ops clk_alpha_pll_slew_ops = {
	.list_rate_vdd_level = clk_list_rate_vdd_level,
#endif
};
EXPORT_SYMBOL(clk_alpha_pll_slew_ops);
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