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Commit 8e66791a authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'pci-v4.15-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci 

Pull PCI fixes from Bjorn Helgaas:
 "Fix AMD boot regression due to 64-bit window conflicting with system
  memory (Christian König)"

* tag 'pci-v4.15-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci:
  x86/PCI: Move and shrink AMD 64-bit window to avoid conflict
  x86/PCI: Add "pci=big_root_window" option for AMD 64-bit windows
parents ed93de84 03a55173

Documentation/admin-guide/kernel-parameters.txt

+6 −0
Original line number Diff line number Diff line
@@ -3097,6 +3097,12 @@ 
		pcie_scan_all	Scan all possible PCIe devices.  Otherwise we

				only look for one device below a PCIe downstream

				port.

		big_root_window	Try to add a big 64bit memory window to the PCIe

				root complex on AMD CPUs. Some GFX hardware

				can resize a BAR to allow access to all VRAM.

				Adding the window is slightly risky (it may

				conflict with unreported devices), so this

				taints the kernel.



	pcie_aspm=	[PCIE] Forcibly enable or disable PCIe Active State Power

			Management.

arch/x86/include/asm/pci_x86.h

+1 −0
Original line number Diff line number Diff line
@@ -38,6 +38,7 @@ do { \ 
#define PCI_NOASSIGN_ROMS	0x80000

#define PCI_ROOT_NO_CRS		0x100000

#define PCI_NOASSIGN_BARS	0x200000

#define PCI_BIG_ROOT_WINDOW	0x400000



extern unsigned int pci_probe;

extern unsigned long pirq_table_addr;

arch/x86/pci/common.c

+5 −0
Original line number Diff line number Diff line
@@ -594,6 +594,11 @@ char *__init pcibios_setup(char *str) 
	} else if (!strcmp(str, "nocrs")) {

		pci_probe |= PCI_ROOT_NO_CRS;

		return NULL;

#ifdef CONFIG_PHYS_ADDR_T_64BIT

	} else if (!strcmp(str, "big_root_window")) {

		pci_probe |= PCI_BIG_ROOT_WINDOW;

		return NULL;

#endif

	} else if (!strcmp(str, "earlydump")) {

		pci_early_dump_regs = 1;

		return NULL;

arch/x86/pci/fixup.c

+18 −11
Original line number Diff line number Diff line
@@ -662,10 +662,14 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2033, quirk_no_aersid); 
 */

static void pci_amd_enable_64bit_bar(struct pci_dev *dev)

{

	unsigned i;

	u32 base, limit, high;

	struct resource *res, *conflict;

	struct pci_dev *other;

	struct resource *res;

	unsigned i;

	int r;



	if (!(pci_probe & PCI_BIG_ROOT_WINDOW))

		return;



	/* Check that we are the only device of that type */

	other = pci_get_device(dev->vendor, dev->device, NULL);
@@ -699,22 +703,25 @@ static void pci_amd_enable_64bit_bar(struct pci_dev *dev) 
	if (!res)

		return;



	/*

	 * Allocate a 256GB window directly below the 0xfd00000000 hardware

	 * limit (see AMD Family 15h Models 30h-3Fh BKDG, sec 2.4.6).

	 */

	res->name = "PCI Bus 0000:00";

	res->flags = IORESOURCE_PREFETCH | IORESOURCE_MEM |

		IORESOURCE_MEM_64 | IORESOURCE_WINDOW;

	res->start = 0x100000000ull;

	res->start = 0xbd00000000ull;

	res->end = 0xfd00000000ull - 1;



	/* Just grab the free area behind system memory for this */

	while ((conflict = request_resource_conflict(&iomem_resource, res))) {

		if (conflict->end >= res->end) {

	r = request_resource(&iomem_resource, res);

	if (r) {

		kfree(res);

		return;

	}

		res->start = conflict->end + 1;

	}



	dev_info(&dev->dev, "adding root bus resource %pR\n", res);

	dev_info(&dev->dev, "adding root bus resource %pR (tainting kernel)\n",

		 res);

	add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);



	base = ((res->start >> 8) & AMD_141b_MMIO_BASE_MMIOBASE_MASK) |

		AMD_141b_MMIO_BASE_RE_MASK | AMD_141b_MMIO_BASE_WE_MASK;