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Commit 8e5bcb78 authored by Nikita Zhandarovich's avatar Nikita Zhandarovich Committed by Greg Kroah-Hartman
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drm/radeon/r600_cs: Fix possible int overflows in r600_cs_check_reg() 



[ Upstream commit 39c960bbf9d9ea862398759e75736cfb68c3446f ]

While improbable, there may be a chance of hitting integer
overflow when the result of radeon_get_ib_value() gets shifted
left.

Avoid it by casting one of the operands to larger data type (u64).

Found by Linux Verification Center (linuxtesting.org) with static
analysis tool SVACE.

Fixes: 1729dd33 ("drm/radeon/kms: r600 CS parser fixes")
Signed-off-by: default avatarNikita Zhandarovich <n.zhandarovich@fintech.ru>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent 5624a3c1

drivers/gpu/drm/radeon/r600_cs.c

+2 −2
Original line number Diff line number Diff line
@@ -1278,7 +1278,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) 
			return -EINVAL;

		}

		tmp = (reg - CB_COLOR0_BASE) / 4;

		track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;

		track->cb_color_bo_offset[tmp] = (u64)radeon_get_ib_value(p, idx) << 8;

		ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

		track->cb_color_base_last[tmp] = ib[idx];

		track->cb_color_bo[tmp] = reloc->robj;
@@ -1305,7 +1305,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) 
					"0x%04X\n", reg);

			return -EINVAL;

		}

		track->htile_offset = radeon_get_ib_value(p, idx) << 8;

		track->htile_offset = (u64)radeon_get_ib_value(p, idx) << 8;

		ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

		track->htile_bo = reloc->robj;

		track->db_dirty = true;