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Commit 8e40a2f9 authored by Ben Dooks's avatar Ben Dooks Committed by Russell King
Browse files

[ARM] 3330/1: S3C24XX - move UPLL to main clock 



Patch from Ben Dooks

Move the UPLL clock registration to the central
clock file, and add an enable method

Signed-off-by: default avatarBen Dooks <ben-linux@fluff.org>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 766636cc

arch/arm/mach-s3c2410/clock.c

+37 −1
Original line number Original line Diff line number Diff line
@@ -38,6 +38,7 @@ 
#include <linux/ioport.h>

#include <linux/ioport.h>

#include <linux/clk.h>

#include <linux/clk.h>

#include <linux/mutex.h>

#include <linux/mutex.h>

#include <linux/delay.h>





#include <asm/hardware.h>

#include <asm/hardware.h>

#include <asm/irq.h>

#include <asm/irq.h>
@@ -200,6 +201,28 @@ EXPORT_SYMBOL(clk_round_rate); 
EXPORT_SYMBOL(clk_set_rate);

EXPORT_SYMBOL(clk_set_rate);

EXPORT_SYMBOL(clk_get_parent);

EXPORT_SYMBOL(clk_get_parent);





/* base clock enable */



static int s3c24xx_upll_enable(struct clk *clk, int enable)

{

	unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);

	unsigned long orig = clkslow;



	if (enable)

		clkslow &= ~S3C2410_CLKSLOW_UCLK_OFF;

	else

		clkslow |= S3C2410_CLKSLOW_UCLK_OFF;



	__raw_writel(clkslow, S3C2410_CLKSLOW);



	/* if we started the UPLL, then allow to settle */



	if (enable && !(orig & S3C2410_CLKSLOW_UCLK_OFF))

		udelay(200);



	return 0;

}



/* base clocks */

/* base clocks */





static struct clk clk_xtal = {

static struct clk clk_xtal = {
@@ -210,6 +233,14 @@ static struct clk clk_xtal = { 
	.ctrlbit	= 0,

	.ctrlbit	= 0,

};

};





static struct clk clk_upll = {

	.name		= "upll",

	.id		= -1,

	.parent		= NULL,

	.enable		= s3c24xx_upll_enable,

	.ctrlbit	= 0,

};



static struct clk clk_f = {

static struct clk clk_f = {

	.name		= "fclk",

	.name		= "fclk",

	.id		= -1,

	.id		= -1,
@@ -262,7 +293,7 @@ struct clk s3c24xx_uclk = { 
};

};









/* clock definitions */

/* standard clock definitions */





static struct clk init_clocks[] = {

static struct clk init_clocks[] = {

	{

	{
@@ -396,6 +427,7 @@ int __init s3c24xx_setup_clocks(unsigned long xtal, 
				unsigned long hclk,

				unsigned long hclk,

				unsigned long pclk)

				unsigned long pclk)

{

{

	unsigned long upllcon = __raw_readl(S3C2410_UPLLCON);

	unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);

	unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);

	struct clk *clkp = init_clocks;

	struct clk *clkp = init_clocks;

	int ptr;

	int ptr;
@@ -406,6 +438,7 @@ int __init s3c24xx_setup_clocks(unsigned long xtal, 
	/* initialise the main system clocks */

	/* initialise the main system clocks */





	clk_xtal.rate = xtal;

	clk_xtal.rate = xtal;

	clk_upll.rate = s3c2410_get_pll(upllcon, xtal);





	clk_h.rate = hclk;

	clk_h.rate = hclk;

	clk_p.rate = pclk;

	clk_p.rate = pclk;
@@ -439,6 +472,9 @@ int __init s3c24xx_setup_clocks(unsigned long xtal, 
	if (s3c24xx_register_clock(&clk_xtal) < 0)

	if (s3c24xx_register_clock(&clk_xtal) < 0)

		printk(KERN_ERR "failed to register master xtal\n");

		printk(KERN_ERR "failed to register master xtal\n");





	if (s3c24xx_register_clock(&clk_upll) < 0)

		printk(KERN_ERR "failed to register upll clock\n");



	if (s3c24xx_register_clock(&clk_f) < 0)

	if (s3c24xx_register_clock(&clk_f) < 0)

		printk(KERN_ERR "failed to register cpu fclk\n");

		printk(KERN_ERR "failed to register cpu fclk\n");

arch/arm/mach-s3c2410/s3c2440-clock.c

+1 −18
Original line number Original line Diff line number Diff line
@@ -45,11 +45,6 @@ 




/* S3C2440 extended clock support */

/* S3C2440 extended clock support */





static struct clk s3c2440_clk_upll = {

	.name		= "upll",

	.id		= -1,

};



static struct clk s3c2440_clk_cam = {

static struct clk s3c2440_clk_cam = {

	.name		= "camif",

	.name		= "camif",

	.id		= -1,

	.id		= -1,
@@ -66,22 +61,11 @@ static struct clk s3c2440_clk_ac97 = { 




static int s3c2440_clk_add(struct sys_device *sysdev)

static int s3c2440_clk_add(struct sys_device *sysdev)

{

{

	unsigned long upllcon = __raw_readl(S3C2410_UPLLCON);

	unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);

	unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);

	struct clk *clk_h;

	struct clk *clk_h;

	struct clk *clk_p;

	struct clk *clk_p;

	struct clk *clk_xtal;



	clk_xtal = clk_get(NULL, "xtal");

	if (IS_ERR(clk_xtal)) {

		printk(KERN_ERR "S3C2440: Failed to get clk_xtal\n");

		return -EINVAL;

	}



	s3c2440_clk_upll.rate = s3c2410_get_pll(upllcon, clk_xtal->rate);





	printk("S3C2440: Clock Support, UPLL %ld.%03ld MHz, DVS %s\n",

	printk("S3C2440: Clock Support, DVS %s\n",

	       print_mhz(s3c2440_clk_upll.rate),

	       (camdivn & S3C2440_CAMDIVN_DVSEN) ? "on" : "off");

	       (camdivn & S3C2440_CAMDIVN_DVSEN) ? "on" : "off");





	clk_p = clk_get(NULL, "pclk");

	clk_p = clk_get(NULL, "pclk");
@@ -97,7 +81,6 @@ static int s3c2440_clk_add(struct sys_device *sysdev) 




	s3c24xx_register_clock(&s3c2440_clk_ac97);

	s3c24xx_register_clock(&s3c2440_clk_ac97);

	s3c24xx_register_clock(&s3c2440_clk_cam);

	s3c24xx_register_clock(&s3c2440_clk_cam);

	s3c24xx_register_clock(&s3c2440_clk_upll);





	clk_disable(&s3c2440_clk_ac97);

	clk_disable(&s3c2440_clk_ac97);

	clk_disable(&s3c2440_clk_cam);

	clk_disable(&s3c2440_clk_cam);