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Commit 8e0b5e5a authored by Puranam V G Tejaswi's avatar Puranam V G Tejaswi
Browse files

msm: kgsl: Move deassert_gbif_halt to a6xx specific space 



deassert_gbif_halt is needed only for the a6xx targets that use
clear_pending_transactions. So move deassert_gbif_halt to a6xx specific
space. This helps to provide some clarity and avoid gmu and gbif
related checks.

Change-Id: If46fa22a54737c2dbc35205318ed75ead351760a
Signed-off-by: default avatarPuranam V G Tejaswi <pvgtejas@codeaurora.org>
parent b2cdc0d7

drivers/gpu/msm/adreno.c

+0 −12
Original line number Diff line number Diff line
@@ -2031,18 +2031,6 @@ static int _adreno_start(struct adreno_device *adreno_dev) 
	if (regulator_left_on)

		_soft_reset(adreno_dev);



	/*

	 * During adreno_stop, GBIF halt is asserted to ensure

	 * no further transaction can go through GPU before GPU

	 * headswitch is turned off.

	 *

	 * This halt is deasserted once headswitch goes off but

	 * incase headswitch doesn't goes off clear GBIF halt

	 * here to ensure GPU wake-up doesn't fail because of

	 * halted GPU transactions.

	 */

	adreno_deassert_gbif_halt(adreno_dev);



	adreno_ringbuffer_set_global(adreno_dev, 0);



	status = kgsl_mmu_start(device);

drivers/gpu/msm/adreno.h

+0 −18
Original line number Diff line number Diff line
@@ -696,9 +696,7 @@ enum adreno_regs { 
	ADRENO_REG_RBBM_PERFCTR_RBBM_0_HI,

	ADRENO_REG_RBBM_PERFCTR_LOAD_VALUE_LO,

	ADRENO_REG_RBBM_PERFCTR_LOAD_VALUE_HI,

	ADRENO_REG_GBIF_HALT,

	ADRENO_REG_VBIF_VERSION,

	ADRENO_REG_RBBM_GBIF_HALT,

	ADRENO_REG_GMU_AO_HOST_INTERRUPT_MASK,

	ADRENO_REG_GMU_AHB_FENCE_STATUS,

	ADRENO_REG_GMU_GMU2HOST_INTR_MASK,
@@ -1692,22 +1690,6 @@ static inline int adreno_wait_for_halt_ack(struct kgsl_device *device, 
	return 0;

}



static inline void adreno_deassert_gbif_halt(struct adreno_device *adreno_dev)

{

	if (adreno_has_gbif(adreno_dev)) {

		adreno_writereg(adreno_dev, ADRENO_REG_GBIF_HALT, 0x0);



		/*

		 * Release GBIF GX halt. For A615 family, GPU GX halt

		 * will be cleared automatically on reset.

		 */

		if (!gmu_core_gpmu_isenabled(KGSL_DEVICE(adreno_dev)) &&

			!adreno_is_a615_family(adreno_dev))

			adreno_writereg(adreno_dev,

				ADRENO_REG_RBBM_GBIF_HALT, 0x0);

	}

}



/**

 * adreno_move_preempt_state - Update the preemption state

 * @adreno_dev: An Adreno GPU device handle

drivers/gpu/msm/adreno_a6xx.c

+25 −3
Original line number Diff line number Diff line
@@ -426,6 +426,18 @@ static void a6xx_set_secvid(struct kgsl_device *device) 
		set = true;

}



static void a6xx_deassert_gbif_halt(struct adreno_device *adreno_dev)

{

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);



	kgsl_regwrite(device, A6XX_GBIF_HALT, 0x0);



	if (adreno_is_a619_holi(adreno_dev))

		kgsl_regwrite(device, A6XX_RBBM_GPR0_CNTL, 0x0);

	else

		kgsl_regwrite(device, A6XX_RBBM_GBIF_HALT, 0x0);

}



/*

 * Some targets support marking certain transactions as always privileged which

 * allows us to mark more memory as privileged without having to explicitly set
@@ -696,6 +708,19 @@ void a6xx_start(struct adreno_device *adreno_dev) 
		a6xx_patch_pwrup_reglist(adreno_dev);

		patch_reglist = true;

	}



	/*

	 * During adreno_stop, GBIF halt is asserted to ensure

	 * no further transaction can go through GPU before GPU

	 * headswitch is turned off.

	 *

	 * This halt is deasserted once headswitch goes off but

	 * incase headswitch doesn't goes off clear GBIF halt

	 * here to ensure GPU wake-up doesn't fail because of

	 * halted GPU transactions.

	 */

	a6xx_deassert_gbif_halt(adreno_dev);



}



/* Offsets into the MX/CX mapped register regions */
@@ -2300,9 +2325,6 @@ static unsigned int a6xx_register_offsets[ADRENO_REG_REGISTER_MAX] = { 
	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_PERFCTR_LOAD_VALUE_HI,

				A6XX_RBBM_PERFCTR_LOAD_VALUE_HI),

	ADRENO_REG_DEFINE(ADRENO_REG_VBIF_VERSION, A6XX_VBIF_VERSION),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_GBIF_HALT,

				A6XX_RBBM_GBIF_HALT),

	ADRENO_REG_DEFINE(ADRENO_REG_GBIF_HALT, A6XX_GBIF_HALT),

	ADRENO_REG_DEFINE(ADRENO_REG_GMU_AO_HOST_INTERRUPT_MASK,

				A6XX_GMU_AO_HOST_INTERRUPT_MASK),

	ADRENO_REG_DEFINE(ADRENO_REG_GMU_AHB_FENCE_STATUS,