Merge "pinctrl: qcom: Add blair tlmm spare registers" (8de67093) · Commits · e / devices / android_kernel_fairphone_FP5

drivers/pinctrl/qcom/pinctrl-blair.c

+27 −0

Original line number	Diff line number	Diff line
		@@ -118,7 +118,23 @@
		.offset = qup_offset, \
		}

		#define TLMM_NORTH_SPARE_OFFSET 0x1B3000
		#define TLMM_NORTH_SPARE1_OFFSET 0x1B4000

		#define SPARE_REG(sparereg, spare_offset) \
		{ \
		.spare_reg = tlmm_##sparereg, \
		.offset = spare_offset, \
		}

		enum blair_tlmm_spare {
		tlmm_west_spare,
		tlmm_west_spare1,
		tlmm_north_spare,
		tlmm_north_spare1,
		tlmm_south_spare,
		tlmm_south_spare1,
		};

		static const struct pinctrl_pin_desc blair_pins[] = {
		PINCTRL_PIN(0, "GPIO_0"),
		@@ -1312,6 +1328,15 @@ static const struct msm_function blair_functions[] = {
		FUNCTION(USB_PHY),
		};

		static const struct msm_spare_tlmm blair_spare_regs[] = {
		SPARE_REG(west_spare, 0),
		SPARE_REG(west_spare1, 0),
		SPARE_REG(north_spare, TLMM_NORTH_SPARE_OFFSET),
		SPARE_REG(north_spare1, TLMM_NORTH_SPARE1_OFFSET),
		SPARE_REG(south_spare, 0),
		SPARE_REG(south_spare1, 0),
		};

		/* Every pin is maintained as a single group, and missing or non-existing pin
		* would be maintained as dummy group to synchronize pin group index with
		* pin descriptor registered with pinctrl core.
		@@ -1652,6 +1677,8 @@ static const struct msm_pinctrl_soc_data blair_pinctrl = {
		.ngpios = 157,
		.wakeirq_map = blair_mpm_map,
		.nwakeirq_map = ARRAY_SIZE(blair_mpm_map),
		.spare_regs = blair_spare_regs,
		.nspare_regs = ARRAY_SIZE(blair_spare_regs),
		};

		static int blair_pinctrl_probe(struct platform_device *pdev)

+40 −0

Original line number	Diff line number	Diff line
		@@ -37,6 +37,7 @@
		#define MAX_NR_TILES 4
		#define PS_HOLD_OFFSET 0x820
		#define QUP_MASK GENMASK(5, 0)
		#define SPARE_MASK GENMASK(15, 8)

		/**
		* struct msm_pinctrl - state for a pinctrl-msm device
		@@ -1505,6 +1506,45 @@ int msm_qup_read(unsigned int mode)
		return -ENOENT;
		}

		int msm_spare_write(int spare_reg, u32 val)
		{
		u32 offset;
		const struct msm_spare_tlmm *regs = msm_pinctrl_data->soc->spare_regs;
		int num_regs = msm_pinctrl_data->soc->nspare_regs;

		if (!regs \|\| spare_reg >= num_regs)
		return -ENOENT;

		offset = regs[spare_reg].offset;
		if (offset != 0) {
		writel_relaxed(val & SPARE_MASK,
		msm_pinctrl_data->regs[0] + offset);
		return 0;
		}

		return -ENOENT;
		}
		EXPORT_SYMBOL(msm_spare_write);

		int msm_spare_read(int spare_reg)
		{
		u32 offset, val;
		const struct msm_spare_tlmm *regs = msm_pinctrl_data->soc->spare_regs;
		int num_regs = msm_pinctrl_data->soc->nspare_regs;

		if (!regs \|\| spare_reg >= num_regs)
		return -ENOENT;

		offset = regs[spare_reg].offset;
		if (offset != 0) {
		val = readl_relaxed(msm_pinctrl_data->regs[0] + offset);
		return val & SPARE_MASK;
		}

		return -ENOENT;
		}
		EXPORT_SYMBOL(msm_spare_read);

		/*
		* msm_gpio_mpm_wake_set - API to make interrupt wakeup capable
		* @dev: Device corrsponding to pinctrl

+12 −0

Original line number	Diff line number	Diff line
		@@ -125,6 +125,16 @@ struct pinctrl_qup {
		u32 offset;
		};

		/*
		* struct msm_spare_tlmm - TLMM spare registers config
		* @spare_reg: spare register number
		* @offset: Offset of spare register
		*/
		struct msm_spare_tlmm {
		int spare_reg;
		u32 offset;
		};

		/**
		* struct msm_gpio_wakeirq_map - Map of GPIOs and their wakeup pins
		* @gpio: The GPIOs that are wakeup capable
		@@ -169,6 +179,8 @@ struct msm_pinctrl_soc_data {
		unsigned int n_no_wake_gpios;
		struct pinctrl_qup *qup_regs;
		unsigned int nqup_regs;
		const struct msm_spare_tlmm *spare_regs;
		unsigned int nspare_regs;
		struct msm_dir_conn *dir_conn;
		};

+5 −1

Original line number	Diff line number	Diff line
		/* SPDX-License-Identifier: GPL-2.0-only */
		/*
		* Copyright (c) 2019, The Linux Foundation. All rights reserved.
		* Copyright (c) 2019,2021 The Linux Foundation. All rights reserved.
		*/

		#ifndef __LINUX_PINCTRL_MSM_H__
		@@ -15,4 +15,8 @@ int msm_qup_read(u32 mode);
		/* API to write to mpm_wakeup registers */
		int msm_gpio_mpm_wake_set(unsigned int gpio, bool enable);

		/* APIS to TLMM Spare registers */
		int msm_spare_write(int spare_reg, u32 val);
		int msm_spare_read(int spare_reg);

		#endif /* __LINUX_PINCTRL_MSM_H__ */