Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 8dd34523 authored by Rohith Kollalsi's avatar Rohith Kollalsi
Browse files

ARM: dts: msm: Add Superspeed PHY node on sdxnightjar 

Add Superspeed PHY node and the corresponding resources
to support USB superspeed on sdxnightjar.

Change-Id: Ib41978095f544b3dac76109274c31778ce6ba6af
parent a8772424

qcom/sdxnightjar-usb.dtsi

+104 −2
Original line number Diff line number Diff line
@@ -42,7 +42,7 @@ 
			compatible = "snps,dwc3";

			reg = <0x08a00000 0xcd00>;

			interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;

			usb-phy = <&qusb_phy>, <&usb_nop_phy>;

			usb-phy = <&qusb_phy>, <&ssphy>;

			tx-fifo-resize;

			snps,is-utmi-l1-suspend;

			snps,hird-threshold = /bits/ 8 <0x0>;
@@ -50,7 +50,7 @@ 
			snps,dis-u1-entry-quirk;

			snps,dis-u2-entry-quirk;

			xhci-imod-value = <4000>;

			maximum-speed = "high-speed";

			maximum-speed = "super-speed";

			dr_mode = "otg";

		};

	};
@@ -87,6 +87,108 @@ 
		reset-names = "phy_reset";

	};



	ssphy: ssphy@78000 {

		compatible = "qcom,usb-ssphy-qmp";

		reg = <0x00078000 0x9f8>,

		      <0x01947244 0x4>;

		reg-names = "qmp_phy_base",

			    "vls_clamp_reg";

		qcom,qmp-phy-init-seq = <0xac 0x14 0x00

					0x34 0x08 0x00

					0x174 0x30 0x00

					0x3c 0x06 0x00

					0xb4 0x00 0x00

					0xb8 0x08 0x00

					0x194 0x06 0x3e8

					0x19c 0x01 0x00

					0x178 0x00 0x00

					0xd0 0x82 0x00

					0xdc 0x55 0x00

					0xe0 0x55 0x00

					0xe4 0x03 0x00

					0x78 0x0b 0x00

					0x84 0x16 0x00

					0x90 0x28 0x00

					0x108 0x80 0x00

					0x10c 0x00 0x00

					0x184 0x0a 0x00

					0x4c 0x15 0x00

					0x50 0x34 0x00

					0x54 0x00 0x00

					0xc8 0x00 0x00

					0x18c 0x00 0x00

					0xcc 0x00 0x00

					0x128 0x00 0x00

					0x0c 0x0a 0x00

					0x10 0x01 0x00

					0x1c 0x31 0x00

					0x20 0x01 0x00

					0x14 0x00 0x00

					0x18 0x00 0x00

					0x24 0xde 0x00

					0x28 0x07 0x00

					0x48 0x0f 0x00

					0x70 0x0f 0x00

					0x100 0x80 0x00

					0x440 0x0b 0x00

					0x4d8 0x02 0x00

					0x4dc 0x6c 0x00

					0x4e0 0xbb 0x00

					0x508 0x77 0x00

					0x50c 0x80 0x00

					0x514 0x03 0x00

					0x51c 0x16 0x00

					0x448 0x75 0x00

					0x454 0x00 0x00

					0x40c 0x0a 0x00

					0x41c 0x06 0x00

					0x510 0x00 0x00

					0x268 0x45 0x00

					0x2ac 0x12 0x00

					0x294 0x06 0x00

					0x254 0x00 0x00

					0x8c8 0x83 0x00

					0x8c4 0x02 0x00

					0x8cc 0x09 0x00

					0x8d0 0xa2 0x00

					0x8d4 0x85 0x00

					0x880 0xd1 0x00

					0x884 0x1f 0x00

					0x888 0x47 0x00

					0x80c 0x9f 0x00

					0x824 0x17 0x00

					0x828 0x0f 0x00

					0x8b8 0x75 0x00

					0x8bc 0x13 0x00

					0x8b0 0x86 0x00

					0x8a0 0x04 0x00

					0x88c 0x44 0x00

					0x870 0xe7 0x00

					0x874 0x03 0x00

					0x878 0x40 0x00

					0x87c 0x00 0x00

					0x9d8 0x88 0x00

					0xffffffff 0xffffffff 0x00>;

		qcom,qmp-phy-reg-offset = <0x974 0x8d8 0x8dc 0x804 0x800

					0x808>;

		vdd-supply = <&pmd9650_l4>;

		core-supply = <&pmd9650_l5>;

		qcom,vdd-voltage-level = <0 928000 928000>;

		qcom,core-voltage-level = <0 1800000 1800000>;



		clocks = <&gcc GCC_USB3_AUX_CLK>,

			 <&gcc GCC_USB3_PIPE_CLK>,

			 <&gcc GCC_USB_PHY_CFG_AHB_CLK>,

			 <&rpmcc RPM_SMD_LN_BB_CLK>,

			 <&gcc GCC_USB_SS_REF_CLK>;



		clock-names = "aux_clk", "pipe_clk", "cfg_ahb_clk",

			      "ref_clk_src", "ref_clk";

		resets = <&gcc GCC_USB3_PHY_BCR>,

			 <&gcc GCC_USB3PHY_PHY_BCR>;

		reset-names = "phy_reset", "phy_phy_reset";

	};



	usb_nop_phy: usb_nop_phy {

		compatible = "usb-nop-xceiv";

	};