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Commit 8dd2eee2 authored by Thomas Gleixner's avatar Thomas Gleixner
Browse files

Merge branch 'clockevents/5.1' of... 

Merge branch 'clockevents/5.1' of https://git.linaro.org/people/daniel.lezcano/linux into timers/core

Pull clockevents updates from Daniel Lezcano:

 - Update the binding documentation for the gpt timer (Anson Huang)

 - Improve checking and error handling at init time on risc timer (Atish
   Patra)

 - Update the binding documentation for r8a774c0 cmt and tmu (Biju Das)

 - Fail gracefully when clock rate is unavailable on sun5i (Chen-Yu Tsai)

 - Rename the tango-xtal, pxa and cs5535 to timer-*.c for consistency
   (Daniel Lezcano)

 - Add the support for the tegra210 timer and add the platform's Kconfig
   selection (Joseph Lo)

 - Do a cleanup in the header inclusions and remove the unused ones for the
   exynos_mct timer driver (Krzysztof Kozlowski)

 - Remove some non-of dead code and fix the error path when initializing
   the resources in the exynos_mct timer driver (Marek Szyprowski)

 - Update the DT bindings for the MT7629 (Ryder Lee)

 - Provide a workaround for the arm arch timer for Allwinner A64 timers
   (Samuel Holland)

 - Clear the timer interrupt at shutdown time on the exynos_mct timer
   driver (Stuart Menefy)
parents 75b710af f40f4fc9

Documentation/arm64/silicon-errata.txt

+2 −0
Original line number Diff line number Diff line
@@ -44,6 +44,8 @@ stable kernels. 


| Implementor    | Component       | Erratum ID      | Kconfig                     |

+----------------+-----------------+-----------------+-----------------------------+

| Allwinner      | A64/R18         | UNKNOWN1        | SUN50I_ERRATUM_UNKNOWN1     |

|                |                 |                 |                             |

| ARM            | Cortex-A53      | #826319         | ARM64_ERRATUM_826319        |

| ARM            | Cortex-A53      | #827319         | ARM64_ERRATUM_827319        |

| ARM            | Cortex-A53      | #824069         | ARM64_ERRATUM_824069        |

Documentation/devicetree/bindings/timer/fsl,imxgpt.txt

+33 −6
Original line number Diff line number Diff line
@@ -2,17 +2,44 @@ Freescale i.MX General Purpose Timer (GPT) 


Required properties:



- compatible : should be "fsl,<soc>-gpt"

- reg : Specifies base physical address and size of the registers.

- interrupts : A list of 4 interrupts; one per timer channel.

- clocks : The clocks provided by the SoC to drive the timer.

- compatible : should be one of following:

  for i.MX1:

  - "fsl,imx1-gpt";

  for i.MX21:

  - "fsl,imx21-gpt";

  for i.MX27:

  - "fsl,imx27-gpt", "fsl,imx21-gpt";

  for i.MX31:

  - "fsl,imx31-gpt";

  for i.MX25:

  - "fsl,imx25-gpt", "fsl,imx31-gpt";

  for i.MX50:

  - "fsl,imx50-gpt", "fsl,imx31-gpt";

  for i.MX51:

  - "fsl,imx51-gpt", "fsl,imx31-gpt";

  for i.MX53:

  - "fsl,imx53-gpt", "fsl,imx31-gpt";

  for i.MX6Q:

  - "fsl,imx6q-gpt", "fsl,imx31-gpt";

  for i.MX6DL:

  - "fsl,imx6dl-gpt";

  for i.MX6SL:

  - "fsl,imx6sl-gpt", "fsl,imx6dl-gpt";

  for i.MX6SX:

  - "fsl,imx6sx-gpt", "fsl,imx6dl-gpt";

- reg : specifies base physical address and size of the registers.

- interrupts : should be the gpt interrupt.

- clocks : the clocks provided by the SoC to drive the timer, must contain

           an entry for each entry in clock-names.

- clock-names : must include "ipg" entry first, then "per" entry.



Example:



gpt1: timer@10003000 {

	compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";

	compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";

	reg = <0x10003000 0x1000>;

	interrupts = <26>;

	clocks = <&clks 46>, <&clks 61>;

	clocks = <&clks IMX27_CLK_GPT1_IPG_GATE>,

		 <&clks IMX27_CLK_PER1_GATE>;

	clock-names = "ipg", "per";

};

Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt

+8 −3
Original line number Diff line number Diff line 
Mediatek Timers

MediaTek Timers

---------------



Mediatek SoCs have two different timers on different platforms,

MediaTek SoCs have two different timers on different platforms,

- GPT (General Purpose Timer)

- SYST (System Timer)
@@ -9,6 +9,7 @@ The proper timer will be selected automatically by driver. 


Required properties:

- compatible should contain:

	For those SoCs that use GPT

	* "mediatek,mt2701-timer" for MT2701 compatible timers (GPT)

	* "mediatek,mt6580-timer" for MT6580 compatible timers (GPT)

	* "mediatek,mt6589-timer" for MT6589 compatible timers (GPT)
@@ -17,7 +18,11 @@ Required properties: 
	* "mediatek,mt8135-timer" for MT8135 compatible timers (GPT)

	* "mediatek,mt8173-timer" for MT8173 compatible timers (GPT)

	* "mediatek,mt6577-timer" for MT6577 and all above compatible timers (GPT)

	* "mediatek,mt6765-timer" for MT6765 compatible timers (SYST)



	For those SoCs that use SYST

	* "mediatek,mt7629-timer" for MT7629 compatible timers (SYST)

	* "mediatek,mt6765-timer" for MT6765 and all above compatible timers (SYST)



- reg: Should contain location and length for timer register.

- clocks: Should contain system clock.

Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt

0 → 100644
+36 −0
Original line number Diff line number Diff line 
NVIDIA Tegra210 timer



The Tegra210 timer provides fourteen 29-bit timer counters and one 32-bit

timestamp counter. The TMRs run at either a fixed 1 MHz clock rate derived

from the oscillator clock (TMR0-TMR9) or directly at the oscillator clock

(TMR10-TMR13). Each TMR can be programmed to generate one-shot, periodic,

or watchdog interrupts.



Required properties:

- compatible : "nvidia,tegra210-timer".

- reg : Specifies base physical address and size of the registers.

- interrupts : A list of 14 interrupts; one per each timer channels 0 through

  13.

- clocks : Must contain one entry, for the module clock.

  See ../clocks/clock-bindings.txt for details.



timer@60005000 {

	compatible = "nvidia,tegra210-timer";

	reg = <0x0 0x60005000 0x0 0x400>;

	interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;

	clocks = <&tegra_car TEGRA210_CLK_TIMER>;

	clock-names = "timer";

};

Documentation/devicetree/bindings/timer/renesas,cmt.txt

+2 −0
Original line number Diff line number Diff line
@@ -32,6 +32,8 @@ Required Properties: 
    - "renesas,r8a77470-cmt1" for the 48-bit CMT1 device included in r8a77470.

    - "renesas,r8a774a1-cmt0" for the 32-bit CMT0 device included in r8a774a1.

    - "renesas,r8a774a1-cmt1" for the 48-bit CMT1 device included in r8a774a1.

    - "renesas,r8a774c0-cmt0" for the 32-bit CMT0 device included in r8a774c0.

    - "renesas,r8a774c0-cmt1" for the 48-bit CMT1 device included in r8a774c0.

    - "renesas,r8a7790-cmt0" for the 32-bit CMT0 device included in r8a7790.

    - "renesas,r8a7790-cmt1" for the 48-bit CMT1 device included in r8a7790.

    - "renesas,r8a7791-cmt0" for the 32-bit CMT0 device included in r8a7791.