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Commit 8d99704f authored by Thierry Reding's avatar Thierry Reding
Browse files

clk: tegra: Format tables consistently 



Use spaces around { and } and pad values so that the cells are properly
aligned.

Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent e52d7c04

drivers/clk/tegra/clk-tegra114.c

+137 −136
Original line number Diff line number Diff line
@@ -202,12 +202,12 @@ static struct pdiv_map pllxc_p[] = { 
};



static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {

	{ 12000000, 624000000, 104, 0, 2},

	{ 12000000, 600000000, 100, 0, 2},

	{ 13000000, 600000000,  92, 0, 2},	/* actual: 598.0 MHz */

	{ 16800000, 600000000,  71, 0, 2},	/* actual: 596.4 MHz */

	{ 19200000, 600000000,  62, 0, 2},	/* actual: 595.2 MHz */

	{ 26000000, 600000000,  92, 1, 2},	/* actual: 598.0 MHz */

	{ 12000000, 624000000, 104, 0, 2, 0 },

	{ 12000000, 600000000, 100, 0, 2, 0 },

	{ 13000000, 600000000,  92, 0, 2, 0 }, /* actual: 598.0 MHz */

	{ 16800000, 600000000,  71, 0, 2, 0 }, /* actual: 596.4 MHz */

	{ 19200000, 600000000,  62, 0, 2, 0 }, /* actual: 595.2 MHz */

	{ 26000000, 600000000,  92, 1, 2, 0 }, /* actual: 598.0 MHz */

	{        0,         0,   0, 0, 0, 0 },

};
@@ -254,11 +254,11 @@ static struct pdiv_map pllc_p[] = { 
};



static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = {

	{12000000, 600000000, 100, 0, 2},

	{13000000, 600000000, 92, 0, 2},	/* actual: 598.0 MHz */

	{16800000, 600000000, 71, 0, 2},	/* actual: 596.4 MHz */

	{19200000, 600000000, 62, 0, 2},	/* actual: 595.2 MHz */

	{26000000, 600000000, 92, 1, 2},	/* actual: 598.0 MHz */

	{ 12000000, 600000000, 100, 0, 2, 0 },

	{ 13000000, 600000000,  92, 0, 2, 0 }, /* actual: 598.0 MHz */

	{ 16800000, 600000000,  71, 0, 2, 0 }, /* actual: 596.4 MHz */

	{ 19200000, 600000000,  62, 0, 2, 0 }, /* actual: 595.2 MHz */

	{ 26000000, 600000000,  92, 1, 2, 0 }, /* actual: 598.0 MHz */

	{        0,         0,   0, 0, 0, 0 },

};
@@ -325,11 +325,11 @@ static struct pdiv_map pllm_p[] = { 
};



static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {

	{12000000, 800000000, 66, 0, 1},	/* actual: 792.0 MHz */

	{13000000, 800000000, 61, 0, 1},	/* actual: 793.0 MHz */

	{16800000, 800000000, 47, 0, 1},	/* actual: 789.6 MHz */

	{19200000, 800000000, 41, 0, 1},	/* actual: 787.2 MHz */

	{26000000, 800000000, 61, 1, 1},	/* actual: 793.0 MHz */

	{ 12000000, 800000000, 66, 0, 1, 0 }, /* actual: 792.0 MHz */

	{ 13000000, 800000000, 61, 0, 1, 0 }, /* actual: 793.0 MHz */

	{ 16800000, 800000000, 47, 0, 1, 0 }, /* actual: 789.6 MHz */

	{ 19200000, 800000000, 41, 0, 1, 0 }, /* actual: 787.2 MHz */

	{ 26000000, 800000000, 61, 1, 1, 0 }, /* actual: 793.0 MHz */

	{        0,         0,  0, 0, 0, 0 },

};
@@ -394,7 +394,6 @@ static struct tegra_clk_pll_freq_table pll_a_freq_table[] = { 
	{  9600000, 282240000, 147,  5, 0, 4 },

	{  9600000, 368640000, 192,  5, 0, 4 },

	{  9600000, 240000000, 200,  8, 0, 8 },



	{ 28800000, 282240000, 245, 25, 0, 8 },

	{ 28800000, 368640000, 320, 25, 0, 8 },

	{ 28800000, 240000000, 200, 24, 0, 8 },
@@ -425,18 +424,15 @@ static struct tegra_clk_pll_freq_table pll_d_freq_table[] = { 
	{ 16800000,  216000000,  720, 14, 2, 12 },

	{ 19200000,  216000000,  720, 16, 2, 12 },

	{ 26000000,  216000000,  864, 26, 2, 12 },



	{ 12000000,  594000000,  594, 12, 0, 12 },

	{ 13000000,  594000000,  594, 13, 0, 12 },

	{ 16800000,  594000000,  495, 14, 0, 12 },

	{ 19200000,  594000000,  495, 16, 0, 12 },

	{ 26000000,  594000000,  594, 26, 0, 12 },



	{ 12000000, 1000000000, 1000, 12, 0, 12 },

	{ 13000000, 1000000000, 1000, 13, 0, 12 },

	{ 19200000, 1000000000,  625, 12, 0, 12 },

	{ 26000000, 1000000000, 1000, 26, 0, 12 },



	{        0,          0,    0,  0, 0,  0 },

};
@@ -521,12 +517,11 @@ static struct tegra_clk_pll_params pll_u_params = { 


static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {

	/* 1 GHz */

	{12000000, 1000000000, 83, 0, 1},	/* actual: 996.0 MHz */

	{13000000, 1000000000, 76, 0, 1},	/* actual: 988.0 MHz */

	{16800000, 1000000000, 59, 0, 1},	/* actual: 991.2 MHz */

	{19200000, 1000000000, 52, 0, 1},	/* actual: 998.4 MHz */

	{26000000, 1000000000, 76, 1, 1},	/* actual: 988.0 MHz */



	{ 12000000, 1000000000, 83, 0, 1, 0 }, /* actual: 996.0 MHz */

	{ 13000000, 1000000000, 76, 0, 1, 0 }, /* actual: 988.0 MHz */

	{ 16800000, 1000000000, 59, 0, 1, 0 }, /* actual: 991.2 MHz */

	{ 19200000, 1000000000, 52, 0, 1, 0 }, /* actual: 998.4 MHz */

	{ 26000000, 1000000000, 76, 1, 1, 0 }, /* actual: 988.0 MHz */

	{        0,          0,  0, 0, 0, 0 },

};
@@ -644,21 +639,27 @@ struct utmi_clk_param { 
};



static const struct utmi_clk_param utmi_parameters[] = {

	{.osc_frequency = 13000000, .enable_delay_count = 0x02,

	{

		.osc_frequency = 13000000, .enable_delay_count = 0x02,

		.stable_count = 0x33, .active_delay_count = 0x05,

	 .xtal_freq_count = 0x7F},

	{.osc_frequency = 19200000, .enable_delay_count = 0x03,

	 .stable_count = 0x4B, .active_delay_count = 0x06,

	 .xtal_freq_count = 0xBB},

	{.osc_frequency = 12000000, .enable_delay_count = 0x02,

	 .stable_count = 0x2F, .active_delay_count = 0x04,

	 .xtal_freq_count = 0x76},

	{.osc_frequency = 26000000, .enable_delay_count = 0x04,

		.xtal_freq_count = 0x7f

	}, {

		.osc_frequency = 19200000, .enable_delay_count = 0x03,

		.stable_count = 0x4b, .active_delay_count = 0x06,

		.xtal_freq_count = 0xbb

	}, {

		.osc_frequency = 12000000, .enable_delay_count = 0x02,

		.stable_count = 0x2f, .active_delay_count = 0x04,

		.xtal_freq_count = 0x76

	}, {

		.osc_frequency = 26000000, .enable_delay_count = 0x04,

		.stable_count = 0x66, .active_delay_count = 0x09,

	 .xtal_freq_count = 0xFE},

	{.osc_frequency = 16800000, .enable_delay_count = 0x03,

	 .stable_count = 0x41, .active_delay_count = 0x0A,

	 .xtal_freq_count = 0xA4},

		.xtal_freq_count = 0xfe

	}, {

		.osc_frequency = 16800000, .enable_delay_count = 0x03,

		.stable_count = 0x41, .active_delay_count = 0x0a,

		.xtal_freq_count = 0xa4

	},

};



/* peripheral mux definitions */
@@ -1315,7 +1316,7 @@ static struct tegra_clk_init_table init_table[] __initdata = { 
	{ TEGRA114_CLK_XUSB_HS_SRC, TEGRA114_CLK_XUSB_SS_DIV2, 61200000, 0 },

	{ TEGRA114_CLK_XUSB_FALCON_SRC, TEGRA114_CLK_PLL_P, 204000000, 0 },

	{ TEGRA114_CLK_XUSB_HOST_SRC, TEGRA114_CLK_PLL_P, 102000000, 0 },

	/* This MUST be the last entry. */

	/* must be the last entry */

	{ TEGRA114_CLK_CLK_MAX, TEGRA114_CLK_CLK_MAX, 0, 0 },

};

drivers/clk/tegra/clk-tegra124.c

+186 −184
Original line number Diff line number Diff line
@@ -189,11 +189,11 @@ static struct pdiv_map pllxc_p[] = { 


static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {

	/* 1 GHz */

	{12000000, 1000000000, 83, 0, 1},	/* actual: 996.0 MHz */

	{13000000, 1000000000, 76, 0, 1},	/* actual: 988.0 MHz */

	{16800000, 1000000000, 59, 0, 1},	/* actual: 991.2 MHz */

	{19200000, 1000000000, 52, 0, 1},	/* actual: 998.4 MHz */

	{26000000, 1000000000, 76, 1, 1},	/* actual: 988.0 MHz */

	{ 12000000, 1000000000, 83, 0, 1, 0 }, /* actual: 996.0 MHz */

	{ 13000000, 1000000000, 76, 0, 1, 0 }, /* actual: 988.0 MHz */

	{ 16800000, 1000000000, 59, 0, 1, 0 }, /* actual: 991.2 MHz */

	{ 19200000, 1000000000, 52, 0, 1, 0 }, /* actual: 998.4 MHz */

	{ 26000000, 1000000000, 76, 1, 1, 0 }, /* actual: 988.0 MHz */

	{        0,          0,  0, 0, 0, 0 },

};
@@ -222,12 +222,12 @@ static struct tegra_clk_pll_params pll_x_params = { 
};



static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {

	{ 12000000, 624000000, 104, 1, 2},

	{ 12000000, 600000000, 100, 1, 2},

	{ 13000000, 600000000,  92, 1, 2},	/* actual: 598.0 MHz */

	{ 16800000, 600000000,  71, 1, 2},	/* actual: 596.4 MHz */

	{ 19200000, 600000000,  62, 1, 2},	/* actual: 595.2 MHz */

	{ 26000000, 600000000,  92, 2, 2},	/* actual: 598.0 MHz */

	{ 12000000, 624000000, 104, 1, 2, 0 },

	{ 12000000, 600000000, 100, 1, 2, 0 },

	{ 13000000, 600000000,  92, 1, 2, 0 }, /* actual: 598.0 MHz */

	{ 16800000, 600000000,  71, 1, 2, 0 }, /* actual: 596.4 MHz */

	{ 19200000, 600000000,  62, 1, 2, 0 }, /* actual: 595.2 MHz */

	{ 26000000, 600000000,  92, 2, 2, 0 }, /* actual: 598.0 MHz */

	{        0,         0,   0, 0, 0, 0 },

};
@@ -277,11 +277,11 @@ static struct pdiv_map pllc_p[] = { 
};



static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = {

	{12000000, 600000000, 100, 1, 2},

	{13000000, 600000000, 92, 1, 2},	/* actual: 598.0 MHz */

	{16800000, 600000000, 71, 1, 2},	/* actual: 596.4 MHz */

	{19200000, 600000000, 62, 1, 2},	/* actual: 595.2 MHz */

	{26000000, 600000000, 92, 2, 2},	/* actual: 598.0 MHz */

	{ 12000000, 600000000, 100, 1, 2, 0 },

	{ 13000000, 600000000,  92, 1, 2, 0 }, /* actual: 598.0 MHz */

	{ 16800000, 600000000,  71, 1, 2, 0 }, /* actual: 596.4 MHz */

	{ 19200000, 600000000,  62, 1, 2, 0 }, /* actual: 595.2 MHz */

	{ 26000000, 600000000,  92, 2, 2, 0 }, /* actual: 598.0 MHz */

	{        0,         0,   0, 0, 0, 0 },

};
@@ -358,11 +358,11 @@ static struct pdiv_map pll12g_ssd_esd_p[] = { 
};



static struct tegra_clk_pll_freq_table pll_c4_freq_table[] = {

	{ 12000000, 600000000, 100, 1, 1},

	{ 13000000, 600000000,  92, 1, 1},      /* actual: 598.0 MHz */

	{ 16800000, 600000000,  71, 1, 1},      /* actual: 596.4 MHz */

	{ 19200000, 600000000,  62, 1, 1},      /* actual: 595.2 MHz */

	{ 26000000, 600000000,  92, 2, 1},      /* actual: 598.0 MHz */

	{ 12000000, 600000000, 100, 1, 1, 0 },

	{ 13000000, 600000000,  92, 1, 1, 0 }, /* actual: 598.0 MHz */

	{ 16800000, 600000000,  71, 1, 1, 0 }, /* actual: 596.4 MHz */

	{ 19200000, 600000000,  62, 1, 1, 0 }, /* actual: 595.2 MHz */

	{ 26000000, 600000000,  92, 2, 1, 0 }, /* actual: 598.0 MHz */

	{        0,         0,   0, 0, 0, 0 },

};
@@ -395,11 +395,11 @@ static struct pdiv_map pllm_p[] = { 
};



static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {

	{12000000, 800000000, 66, 1, 1},	/* actual: 792.0 MHz */

	{13000000, 800000000, 61, 1, 1},	/* actual: 793.0 MHz */

	{16800000, 800000000, 47, 1, 1},	/* actual: 789.6 MHz */

	{19200000, 800000000, 41, 1, 1},	/* actual: 787.2 MHz */

	{26000000, 800000000, 61, 2, 1},	/* actual: 793.0 MHz */

	{ 12000000, 800000000, 66, 1, 1, 0 }, /* actual: 792.0 MHz */

	{ 13000000, 800000000, 61, 1, 1, 0 }, /* actual: 793.0 MHz */

	{ 16800000, 800000000, 47, 1, 1, 0 }, /* actual: 789.6 MHz */

	{ 19200000, 800000000, 41, 1, 1, 0 }, /* actual: 787.2 MHz */

	{ 26000000, 800000000, 61, 2, 1, 0 }, /* actual: 793.0 MHz */

	{        0,         0,  0, 0, 0, 0},

};
@@ -550,7 +550,6 @@ static struct tegra_clk_pll_freq_table pll_a_freq_table[] = { 
	{  9600000, 282240000, 147,  5, 0, 4 },

	{  9600000, 368640000, 192,  5, 0, 4 },

	{  9600000, 240000000, 200,  8, 0, 8 },



	{ 28800000, 282240000, 245, 25, 0, 8 },

	{ 28800000, 368640000, 320, 25, 0, 8 },

	{ 28800000, 240000000, 200, 24, 0, 8 },
@@ -589,18 +588,15 @@ static struct tegra_clk_pll_freq_table pll_d_freq_table[] = { 
	{ 16800000,  216000000,  720, 14, 4, 12 },

	{ 19200000,  216000000,  720, 16, 4, 12 },

	{ 26000000,  216000000,  864, 26, 4, 12 },



	{ 12000000,  594000000,  594, 12, 1, 12 },

	{ 13000000,  594000000,  594, 13, 1, 12 },

	{ 16800000,  594000000,  495, 14, 1, 12 },

	{ 19200000,  594000000,  495, 16, 1, 12 },

	{ 26000000,  594000000,  594, 26, 1, 12 },



	{ 12000000, 1000000000, 1000, 12, 1, 12 },

	{ 13000000, 1000000000, 1000, 13, 1, 12 },

	{ 19200000, 1000000000,  625, 12, 1, 12 },

	{ 26000000, 1000000000, 1000, 26, 1, 12 },



	{        0,          0,    0,  0, 0,  0 },

};
@@ -623,11 +619,11 @@ static struct tegra_clk_pll_params pll_d_params = { 
};



static struct tegra_clk_pll_freq_table tegra124_pll_d2_freq_table[] = {

	{ 12000000, 594000000,  99, 1, 2},

	{ 13000000, 594000000,  91, 1, 2},      /* actual: 591.5 MHz */

	{ 16800000, 594000000,  71, 1, 2},      /* actual: 596.4 MHz */

	{ 19200000, 594000000,  62, 1, 2},      /* actual: 595.2 MHz */

	{ 26000000, 594000000,  91, 2, 2},      /* actual: 591.5 MHz */

	{ 12000000, 594000000, 99, 1, 2, 0 },

	{ 13000000, 594000000, 91, 1, 2, 0 }, /* actual: 591.5 MHz */

	{ 16800000, 594000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */

	{ 19200000, 594000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */

	{ 26000000, 594000000, 91, 2, 2, 0 }, /* actual: 591.5 MHz */

	{        0,         0,  0, 0, 0, 0 },

};
@@ -655,11 +651,11 @@ static struct tegra_clk_pll_params tegra124_pll_d2_params = { 
};



static struct tegra_clk_pll_freq_table pll_dp_freq_table[] = {

	{ 12000000, 600000000, 100, 1, 1},

	{ 13000000, 600000000,  92, 1, 1},      /* actual: 598.0 MHz */

	{ 16800000, 600000000,  71, 1, 1},      /* actual: 596.4 MHz */

	{ 19200000, 600000000,  62, 1, 1},      /* actual: 595.2 MHz */

	{ 26000000, 600000000,  92, 2, 1},      /* actual: 598.0 MHz */

	{ 12000000, 600000000, 100, 1, 1, 0 },

	{ 13000000, 600000000,  92, 1, 1, 0 }, /* actual: 598.0 MHz */

	{ 16800000, 600000000,  71, 1, 1, 0 }, /* actual: 596.4 MHz */

	{ 19200000, 600000000,  62, 1, 1, 0 }, /* actual: 595.2 MHz */

	{ 26000000, 600000000,  92, 2, 1, 0 }, /* actual: 598.0 MHz */

	{        0,         0,   0, 0, 0, 0 },

};
@@ -743,21 +739,27 @@ struct utmi_clk_param { 
};



static const struct utmi_clk_param utmi_parameters[] = {

	{.osc_frequency = 13000000, .enable_delay_count = 0x02,

	{

		.osc_frequency = 13000000, .enable_delay_count = 0x02,

		.stable_count = 0x33, .active_delay_count = 0x05,

	 .xtal_freq_count = 0x7F},

	{.osc_frequency = 19200000, .enable_delay_count = 0x03,

	 .stable_count = 0x4B, .active_delay_count = 0x06,

	 .xtal_freq_count = 0xBB},

	{.osc_frequency = 12000000, .enable_delay_count = 0x02,

	 .stable_count = 0x2F, .active_delay_count = 0x04,

	 .xtal_freq_count = 0x76},

	{.osc_frequency = 26000000, .enable_delay_count = 0x04,

		.xtal_freq_count = 0x7f

	}, {

		.osc_frequency = 19200000, .enable_delay_count = 0x03,

		.stable_count = 0x4b, .active_delay_count = 0x06,

		.xtal_freq_count = 0xbb

	}, {

		.osc_frequency = 12000000, .enable_delay_count = 0x02,

		.stable_count = 0x2f, .active_delay_count = 0x04,

		.xtal_freq_count = 0x76

	}, {

		.osc_frequency = 26000000, .enable_delay_count = 0x04,

		.stable_count = 0x66, .active_delay_count = 0x09,

	 .xtal_freq_count = 0xFE},

	{.osc_frequency = 16800000, .enable_delay_count = 0x03,

	 .stable_count = 0x41, .active_delay_count = 0x0A,

	 .xtal_freq_count = 0xA4},

		.xtal_freq_count = 0xfe

	}, {

		.osc_frequency = 16800000, .enable_delay_count = 0x03,

		.stable_count = 0x41, .active_delay_count = 0x0a,

		.xtal_freq_count = 0xa4

	},

};



static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
@@ -1397,7 +1399,7 @@ static struct tegra_clk_init_table common_init_table[] __initdata = { 
	{ TEGRA124_CLK_MSELECT, TEGRA124_CLK_CLK_MAX, 0, 1 },

	{ TEGRA124_CLK_CSITE, TEGRA124_CLK_CLK_MAX, 0, 1 },

	{ TEGRA124_CLK_TSENSOR, TEGRA124_CLK_CLK_M, 400000, 0 },

	/* This MUST be the last entry. */

	/* must be the last entry */

	{ TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0 },

};
@@ -1406,14 +1408,14 @@ static struct tegra_clk_init_table tegra124_init_table[] __initdata = { 
	{ TEGRA124_CLK_CCLK_G, TEGRA124_CLK_CLK_MAX, 0, 1 },

	{ TEGRA124_CLK_HDA, TEGRA124_CLK_PLL_P, 102000000, 0 },

	{ TEGRA124_CLK_HDA2CODEC_2X, TEGRA124_CLK_PLL_P, 48000000, 0 },

	/* This MUST be the last entry. */

	/* must be the last entry */

	{ TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0 },

};



/* Tegra132 requires the SOC_THERM clock to remain active */

static struct tegra_clk_init_table tegra132_init_table[] __initdata = {

	{ TEGRA124_CLK_SOC_THERM, TEGRA124_CLK_PLL_P, 51000000, 1 },

	/* This MUST be the last entry. */

	/* must be the last entry */

	{ TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0 },

};

drivers/clk/tegra/clk-tegra20.c

+134 −143
Original line number Diff line number Diff line
@@ -209,17 +209,14 @@ static struct tegra_clk_pll_freq_table pll_d_freq_table[] = { 
	{ 13000000,  216000000,  216, 13, 0,  4 },

	{ 19200000,  216000000,  135, 12, 0,  3 },

	{ 26000000,  216000000,  216, 26, 0,  4 },



	{ 12000000,  594000000,  594, 12, 0,  8 },

	{ 13000000,  594000000,  594, 13, 0,  8 },

	{ 19200000,  594000000,  495, 16, 0,  8 },

	{ 26000000,  594000000,  594, 26, 0,  8 },



	{ 12000000, 1000000000, 1000, 12, 0, 12 },

	{ 13000000, 1000000000, 1000, 13, 0, 12 },

	{ 19200000, 1000000000,  625, 12, 0,  8 },

	{ 26000000, 1000000000, 1000, 26, 0, 12 },



	{        0,          0,    0,  0, 0,  0 },

};
@@ -237,49 +234,41 @@ static struct tegra_clk_pll_freq_table pll_x_freq_table[] = { 
	{ 13000000, 1000000000, 1000, 13, 0, 12 },

	{ 19200000, 1000000000,  625, 12, 0,  8 },

	{ 26000000, 1000000000, 1000, 26, 0, 12 },



	/* 912 MHz */

	{ 12000000,  912000000,  912, 12, 0, 12 },

	{ 13000000,  912000000,  912, 13, 0, 12 },

	{ 19200000,  912000000,  760, 16, 0,  8 },

	{ 26000000,  912000000,  912, 26, 0, 12 },



	/* 816 MHz */

	{ 12000000,  816000000,  816, 12, 0, 12 },

	{ 13000000,  816000000,  816, 13, 0, 12 },

	{ 19200000,  816000000,  680, 16, 0,  8 },

	{ 26000000,  816000000,  816, 26, 0, 12 },



	/* 760 MHz */

	{ 12000000,  760000000,  760, 12, 0, 12 },

	{ 13000000,  760000000,  760, 13, 0, 12 },

	{ 19200000,  760000000,  950, 24, 0,  8 },

	{ 26000000,  760000000,  760, 26, 0, 12 },



	/* 750 MHz */

	{ 12000000,  750000000,  750, 12, 0, 12 },

	{ 13000000,  750000000,  750, 13, 0, 12 },

	{ 19200000,  750000000,  625, 16, 0,  8 },

	{ 26000000,  750000000,  750, 26, 0, 12 },



	/* 608 MHz */

	{ 12000000,  608000000,  608, 12, 0, 12 },

	{ 13000000,  608000000,  608, 13, 0, 12 },

	{ 19200000,  608000000,  380, 12, 0,  8 },

	{ 26000000,  608000000,  608, 26, 0, 12 },



	/* 456 MHz */

	{ 12000000,  456000000,  456, 12, 0, 12 },

	{ 13000000,  456000000,  456, 13, 0, 12 },

	{ 19200000,  456000000,  380, 16, 0,  8 },

	{ 26000000,  456000000,  456, 26, 0, 12 },



	/* 312 MHz */

	{ 12000000,  312000000,  312, 12, 0, 12 },

	{ 13000000,  312000000,  312, 13, 0, 12 },

	{ 19200000,  312000000,  260, 16, 0,  8 },

	{ 26000000,  312000000,  312, 26, 0, 12 },



	{        0,          0,    0,  0, 0,  0 },

};
@@ -1061,7 +1050,8 @@ static struct tegra_clk_init_table init_table[] __initdata = { 
	{ TEGRA20_CLK_DISP2, TEGRA20_CLK_PLL_P, 600000000, 0 },

	{ TEGRA20_CLK_GR2D, TEGRA20_CLK_PLL_C, 300000000, 0 },

	{ TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 300000000, 0 },

	{TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0}, /* This MUST be the last entry */

	/* must be the last entry */

	{ TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0 },

};



static void __init tegra20_clock_apply_init_table(void)
@@ -1079,7 +1069,8 @@ static struct tegra_clk_duplicate tegra_clk_duplicates[] = { 
	TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD,    "tegra-ehci.0",  NULL),

	TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD,    "tegra-otg",     NULL),

	TEGRA_CLK_DUPLICATE(TEGRA20_CLK_CCLK,    NULL,           "cpu"),

	TEGRA_CLK_DUPLICATE(TEGRA20_CLK_CLK_MAX, NULL, NULL), /* Must be the last entry */

	/* must be the last entry */

	TEGRA_CLK_DUPLICATE(TEGRA20_CLK_CLK_MAX, NULL,            NULL),

};



static const struct of_device_id pmc_match[] __initconst = {

drivers/clk/tegra/clk-tegra30.c

+189 −189
Original line number Diff line number Diff line
@@ -224,12 +224,27 @@ struct utmi_clk_param { 
};



static const struct utmi_clk_param utmi_parameters[] = {

/*	OSC_FREQUENCY, ENABLE_DLY, STABLE_CNT, ACTIVE_DLY, XTAL_FREQ_CNT */

	{13000000,     0x02,       0x33,       0x05,       0x7F},

	{19200000,     0x03,       0x4B,       0x06,       0xBB},

	{12000000,     0x02,       0x2F,       0x04,       0x76},

	{26000000,     0x04,       0x66,       0x09,       0xFE},

	{16800000,     0x03,       0x41,       0x0A,       0xA4},

	{

		.osc_frequency = 13000000, .enable_delay_count = 0x02,

		.stable_count = 0x33, .active_delay_count = 0x05,

		.xtal_freq_count = 0x7f

	}, {

		.osc_frequency = 19200000, .enable_delay_count = 0x03,

		.stable_count = 0x4b, .active_delay_count = 0x06,

		.xtal_freq_count = 0xbb

	}, {

		.osc_frequency = 12000000, .enable_delay_count = 0x02,

		.stable_count = 0x2f, .active_delay_count = 0x04,

		.xtal_freq_count = 0x76

	}, {

		.osc_frequency = 26000000, .enable_delay_count = 0x04,

		.stable_count = 0x66, .active_delay_count = 0x09,

		.xtal_freq_count = 0xfe

	}, {

		.osc_frequency = 16800000, .enable_delay_count = 0x03,

		.stable_count = 0x41, .active_delay_count = 0x0a,

		.xtal_freq_count = 0xa4

	},

};



static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
@@ -238,31 +253,26 @@ static struct tegra_clk_pll_freq_table pll_c_freq_table[] = { 
	{ 16800000, 1040000000, 495,  8, 0, 8 }, /* actual: 1039.5 MHz */

	{ 19200000, 1040000000, 325,  6, 0, 6 },

	{ 26000000, 1040000000, 520, 13, 0, 8 },



	{ 12000000,  832000000, 416,  6, 0, 8 },

	{ 13000000,  832000000, 832, 13, 0, 8 },

	{ 16800000,  832000000, 396,  8, 0, 8 }, /* actual: 831.6 MHz */

	{ 19200000,  832000000, 260,  6, 0, 8 },

	{ 26000000,  832000000, 416, 13, 0, 8 },



	{ 12000000,  624000000, 624, 12, 0, 8 },

	{ 13000000,  624000000, 624, 13, 0, 8 },

	{ 16800000,  600000000, 520, 14, 0, 8 },

	{ 19200000,  624000000, 520, 16, 0, 8 },

	{ 26000000,  624000000, 624, 26, 0, 8 },



	{ 12000000,  600000000, 600, 12, 0, 8 },

	{ 13000000,  600000000, 600, 13, 0, 8 },

	{ 16800000,  600000000, 500, 14, 0, 8 },

	{ 19200000,  600000000, 375, 12, 0, 6 },

	{ 26000000,  600000000, 600, 26, 0, 8 },



	{ 12000000,  520000000, 520, 12, 0, 8 },

	{ 13000000,  520000000, 520, 13, 0, 8 },

	{ 16800000,  520000000, 495, 16, 0, 8 }, /* actual: 519.75 MHz */

	{ 19200000,  520000000, 325, 12, 0, 6 },

	{ 26000000,  520000000, 520, 26, 0, 8 },



	{ 12000000,  416000000, 416, 12, 0, 8 },

	{ 13000000,  416000000, 416, 13, 0, 8 },

	{ 16800000,  416000000, 396, 16, 0, 8 }, /* actual: 415.8 MHz */
@@ -298,7 +308,6 @@ static struct tegra_clk_pll_freq_table pll_a_freq_table[] = { 
	{  9600000, 564480000, 294,  5, 0, 4 },

	{  9600000, 552960000, 288,  5, 0, 4 },

	{  9600000,  24000000,   5,  2, 0, 1 },



	{ 28800000,  56448000,  49, 25, 0, 1 },

	{ 28800000,  73728000,  64, 25, 0, 1 },

	{ 28800000,  24000000,   5,  6, 0, 1 },
@@ -311,18 +320,15 @@ static struct tegra_clk_pll_freq_table pll_d_freq_table[] = { 
	{ 16800000,  216000000,  180, 14, 0,  4 },

	{ 19200000,  216000000,  180, 16, 0,  4 },

	{ 26000000,  216000000,  216, 26, 0,  4 },



	{ 12000000,  594000000,  594, 12, 0,  8 },

	{ 13000000,  594000000,  594, 13, 0,  8 },

	{ 16800000,  594000000,  495, 14, 0,  8 },

	{ 19200000,  594000000,  495, 16, 0,  8 },

	{ 26000000,  594000000,  594, 26, 0,  8 },



	{ 12000000, 1000000000, 1000, 12, 0, 12 },

	{ 13000000, 1000000000, 1000, 13, 0, 12 },

	{ 19200000, 1000000000,  625, 12, 0,  8 },

	{ 26000000, 1000000000, 1000, 26, 0, 12 },



	{        0,          0,    0,  0, 0,  0 },

};
@@ -348,56 +354,48 @@ static struct tegra_clk_pll_freq_table pll_x_freq_table[] = { 
	{ 16800000, 1700000000, 708,   7, 0, 8 }, /* actual: 1699.2 MHz */

	{ 19200000, 1700000000, 885,  10, 0, 8 }, /* actual: 1699.2 MHz */

	{ 26000000, 1700000000, 850,  13, 0, 8 },



	/* 1.6 GHz */

	{ 12000000, 1600000000, 800,   6, 0, 8 },

	{ 13000000, 1600000000, 738,   6, 0, 8 }, /* actual: 1599.0 MHz */

	{ 16800000, 1600000000, 857,   9, 0, 8 }, /* actual: 1599.7 MHz */

	{ 19200000, 1600000000, 500,   6, 0, 8 },

	{ 26000000, 1600000000, 800,  13, 0, 8 },



	/* 1.5 GHz */

	{ 12000000, 1500000000, 750,   6, 0, 8 },

	{ 13000000, 1500000000, 923,   8, 0, 8 }, /* actual: 1499.8 MHz */

	{ 16800000, 1500000000, 625,   7, 0, 8 },

	{ 19200000, 1500000000, 625,   8, 0, 8 },

	{ 26000000, 1500000000, 750,  13, 0, 8 },



	/* 1.4 GHz */

	{ 12000000, 1400000000,  700,  6, 0, 8 },

	{ 13000000, 1400000000,  969,  9, 0, 8 }, /* actual: 1399.7 MHz */

	{ 16800000, 1400000000, 1000, 12, 0, 8 },

	{ 19200000, 1400000000,  875, 12, 0, 8 },

	{ 26000000, 1400000000,  700, 13, 0, 8 },



	/* 1.3 GHz */

	{ 12000000, 1300000000,  975,  9, 0, 8 },

	{ 13000000, 1300000000, 1000, 10, 0, 8 },

	{ 16800000, 1300000000,  928, 12, 0, 8 }, /* actual: 1299.2 MHz */

	{ 19200000, 1300000000,  812, 12, 0, 8 }, /* actual: 1299.2 MHz */

	{ 26000000, 1300000000,  650, 13, 0, 8 },



	/* 1.2 GHz */

	{ 12000000, 1200000000, 1000, 10, 0, 8 },

	{ 13000000, 1200000000,  923, 10, 0, 8 }, /* actual: 1199.9 MHz */

	{ 16800000, 1200000000, 1000, 14, 0, 8 },

	{ 19200000, 1200000000, 1000, 16, 0, 8 },

	{ 26000000, 1200000000,  600, 13, 0, 8 },



	/* 1.1 GHz */

	{ 12000000, 1100000000, 825,   9, 0, 8 },

	{ 13000000, 1100000000, 846,  10, 0, 8 }, /* actual: 1099.8 MHz */

	{ 16800000, 1100000000, 982,  15, 0, 8 }, /* actual: 1099.8 MHz */

	{ 19200000, 1100000000, 859,  15, 0, 8 }, /* actual: 1099.5 MHz */

	{ 26000000, 1100000000, 550,  13, 0, 8 },



	/* 1 GHz */

	{ 12000000, 1000000000, 1000, 12, 0, 8 },

	{ 13000000, 1000000000, 1000, 13, 0, 8 },

	{ 16800000, 1000000000,  833, 14, 0, 8 }, /* actual: 999.6 MHz */

	{ 19200000, 1000000000,  625, 12, 0, 8 },

	{ 26000000, 1000000000, 1000, 26, 0, 8 },



	{        0,          0,    0,  0, 0, 0 },

};
@@ -1368,7 +1366,8 @@ static struct tegra_clk_init_table init_table[] __initdata = { 
	{ TEGRA30_CLK_GR2D, TEGRA30_CLK_PLL_C, 300000000, 0 },

	{ TEGRA30_CLK_GR3D, TEGRA30_CLK_PLL_C, 300000000, 0 },

	{ TEGRA30_CLK_GR3D2, TEGRA30_CLK_PLL_C, 300000000, 0 },

	{TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0}, /* This MUST be the last entry. */

	/* must be the last entry */

	{ TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0 },

};



static void __init tegra30_clock_apply_init_table(void)
@@ -1393,7 +1392,8 @@ static struct tegra_clk_duplicate tegra_clk_duplicates[] = { 
	TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CML1, "tegra_sata_cml", NULL),

	TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CML0, "tegra_pcie", "cml"),

	TEGRA_CLK_DUPLICATE(TEGRA30_CLK_VCP, "nvavp", "vcp"),

	TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CLK_MAX, NULL, NULL), /* MUST be the last entry */

	/* must be the last entry */

	TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CLK_MAX, NULL, NULL),

};



static const struct of_device_id pmc_match[] __initconst = {