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Commit 8d51f3ee authored by Chandan Kumar Jha's avatar Chandan Kumar Jha Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: Add lagoon camera dtsi

Add ICP, IPE, BPS, CDM, SMMU, JPEG, IFE,, CSID nodes
for lagoon camera.

CRs-Fixed: 2571273
Change-Id: Ice517a40a6c01e8a52a96a41fc22e9c4e655b05a
parent 1023dd54
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lagoon-camera.dtsi

0 → 100644
+670 −0
Original line number Diff line number Diff line
#include <dt-bindings/msm/msm-camera.h>

&soc {
	qcom,cam-req-mgr {
		compatible = "qcom,cam-req-mgr";
		status = "ok";
	};

	qcom,cam_smmu {
		compatible = "qcom,msm-cam-smmu";
		status = "ok";
		non-fatal-fault-disabled;

		msm_cam_smmu_lrme {
			compatible = "qcom,msm-cam-smmu-cb";
			iommus = <&apps_smmu 0xD40 0x20>,
				<&apps_smmu 0xD60 0x20>;
			label = "lrme";
			lrme_iova_mem_map: iova-mem-map {
				iova-mem-region-shared {
					/* Shared region is 100MB long */
					iova-region-name = "shared";
					iova-region-start = <0x7400000>;
					iova-region-len = <0x6400000>;
					iova-region-id = <0x1>;
					status = "ok";
				};
				/* IO region is approximately 3.3 GB */
				iova-mem-region-io {
					iova-region-name = "io";
					iova-region-start = <0xd800000>;
					iova-region-len = <0xd2800000>;
					iova-region-id = <0x3>;
					status = "ok";
				};
			};
		};

		msm_cam_smmu_ife {
			compatible = "qcom,msm-cam-smmu-cb";
			iommus = <&apps_smmu 0x820 0xc0>,
				<&apps_smmu 0x840 0x0>,
				<&apps_smmu 0x860 0xc0>,
				<&apps_smmu 0x880 0x0>;
			label = "ife";
			ife_iova_mem_map: iova-mem-map {
				/* IO region is approximately 3.4 GB */
				iova-mem-region-io {
					iova-region-name = "io";
					iova-region-start = <0x7400000>;
					iova-region-len = <0xd8c00000>;
					iova-region-id = <0x3>;
					status = "ok";
				};
			};
		};

		msm_cam_smmu_jpeg {
			compatible = "qcom,msm-cam-smmu-cb";
			iommus = <&apps_smmu 0xD00 0x20>,
				<&apps_smmu 0xD20 0x20>;
			label = "jpeg";
			jpeg_iova_mem_map: iova-mem-map {
				/* IO region is approximately 3.4 GB */
				iova-mem-region-io {
					iova-region-name = "io";
					iova-region-start = <0x7400000>;
					iova-region-len = <0xd8c00000>;
					iova-region-id = <0x3>;
					status = "ok";
				};
			};
		};

		msm_cam_icp_fw {
			compatible = "qcom,msm-cam-smmu-fw-dev";
			label="icp";
			memory-region = <&pil_camera_mem>;
		};

		msm_cam_smmu_icp {
			compatible = "qcom,msm-cam-smmu-cb";
			iommus = <&apps_smmu 0xCA2 0x0>,
				<&apps_smmu 0xCC0 0x20>,
				<&apps_smmu 0xCE0 0x20>;
			label = "icp";
			icp_iova_mem_map: iova-mem-map {
				iova-mem-region-firmware {
					/* Firmware region is 5MB */
					iova-region-name = "firmware";
					iova-region-start = <0x0>;
					iova-region-len = <0x500000>;
					iova-region-id = <0x0>;
					status = "ok";
				};

				iova-mem-region-shared {
					/* Shared region is 150MB long */
					iova-region-name = "shared";
					iova-region-start = <0x7400000>;
					iova-region-len = <0x9600000>;
					iova-region-id = <0x1>;
					iova-granularity = <0x15>;
					status = "ok";
				};

				iova-mem-region-secondary-heap {
					/* Secondary heap region is 1MB long */
					iova-region-name = "secheap";
					iova-region-start = <0x10A00000>;
					iova-region-len = <0x100000>;
					iova-region-id = <0x4>;
					status = "ok";
				};

				iova-mem-region-io {
					/* IO region is approximately 3 GB */
					iova-region-name = "io";
					iova-region-start = <0x10C00000>;
					iova-region-len = <0xCF300000>;
					iova-region-id = <0x3>;
					status = "ok";
				};

				iova-mem-qdss-region {
					/* qdss region is approximately 1MB */
					iova-region-name = "qdss";
					iova-region-start = <0x10B00000>;
					iova-region-len = <0x100000>;
					iova-region-id = <0x5>;
					qdss-phy-addr = <0x16790000>;
					status = "ok";
				};
			};
		};

		msm_cam_smmu_cpas_cdm {
			compatible = "qcom,msm-cam-smmu-cb";
			iommus = <&apps_smmu 0xC80 0x0>;
			label = "cpas-cdm0";
			cpas_cdm_iova_mem_map: iova-mem-map {
				iova-mem-region-io {
					/* IO region is approximately 3.4 GB */
					iova-region-name = "io";
					iova-region-start = <0x7400000>;
					iova-region-len = <0xd8c00000>;
					iova-region-id = <0x3>;
					status = "ok";
				};
			};
		};

		msm_cam_smmu_secure {
			compatible = "qcom,msm-cam-smmu-cb";
			label = "cam-secure";
			qcom,secure-cb;
		};

	};

	qcom,cam-cdm-intf {
		compatible = "qcom,cam-cdm-intf";
		cell-index = <0>;
		label = "cam-cdm-intf";
		num-hw-cdm = <1>;
		cdm-client-names = "vfe",
			"jpegdma",
			"jpegenc",
			"lrmecdm";
		status = "ok";
	};

	qcom,cpas-cdm0@ac48000 {
		cell-index = <0>;
		compatible = "qcom,cam170-cpas-cdm0";
		label = "cpas-cdm";
		reg = <0xac48000 0x1000>;
		reg-names = "cpas-cdm";
		reg-cam-base = <0x48000>;
		interrupts = <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>;
		interrupt-names = "cpas-cdm";
		regulator-names = "camss";
		camss-supply = <&cam_cc_titan_top_gdsc>;
		clock-names =
			"cam_cc_soc_ahb_clk",
			"cam_cc_cpas_ahb_clk",
			"cam_cc_camnoc_axi_clk";
		clocks =
			<&camcc CAM_CC_SOC_AHB_CLK>,
			<&camcc CAM_CC_CPAS_AHB_CLK>,
			<&camcc CAM_CC_CAMNOC_AXI_CLK>;
		clock-rates = <0 0 0>;
		clock-cntl-level = "svs";
		cdm-client-names = "ife";
		status = "ok";
	};

	qcom,cam-isp {
		compatible = "qcom,cam-isp";
		arch-compat = "ife";
		status = "ok";
	};

	cam_csid0: qcom,csid0@acb3000 {
		cell-index = <0>;
		compatible = "qcom,csid170_200";
		reg-names = "csid";
		reg = <0xacb3000 0x1000>;
		reg-cam-base = <0xb3000>;
		interrupt-names = "csid";
		interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>;
		regulator-names = "camss", "ife0";
		camss-supply = <&cam_cc_titan_top_gdsc>;
		ife0-supply = <&cam_cc_ife_0_gdsc>;
		clock-names =
			"ife_csid_clk_src",
			"ife_csid_clk",
			"cphy_rx_clk_src",
			"ife_cphy_rx_clk",
			"ife_clk_src",
			"ife_clk",
			"ife_axi_clk";
		clocks =
			<&camcc CAM_CC_IFE_0_CSID_CLK_SRC>,
			<&camcc CAM_CC_IFE_0_CSID_CLK>,
			<&camcc CAM_CC_CPHY_RX_CLK_SRC>,
			<&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
			<&camcc CAM_CC_IFE_0_CLK_SRC>,
			<&camcc CAM_CC_IFE_0_CLK>,
			<&camcc CAM_CC_IFE_0_AXI_CLK>;
		clock-rates =
			<300000000 0 0 0 320000000 0 0>,
			<384000000 0 0 0 404000000 0 0>,
			<400000000 0 0 0 480000000 0 0>,
			<400000000 0 0 0 600000000 0 0>;
		clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
		src-clock-name = "ife_csid_clk_src";
		status = "ok";
	};

	cam_vfe0: qcom,vfe0@acaf000 {
		cell-index = <0>;
		compatible = "qcom,vfe170_150";
		reg-names = "ife";
		reg = <0xacaf000 0x4000>;
		reg-cam-base = <0xaf000>;
		interrupt-names = "ife";
		interrupts = <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>;
		regulator-names = "camss", "ife0";
		camss-supply = <&cam_cc_titan_top_gdsc>;
		ife0-supply = <&cam_cc_ife_0_gdsc>;
		clock-names =
			"ife_clk_src",
			"ife_clk",
			"ife_axi_clk";
		clocks =
			<&camcc CAM_CC_IFE_0_CLK_SRC>,
			<&camcc CAM_CC_IFE_0_CLK>,
			<&camcc CAM_CC_IFE_0_AXI_CLK>;
		clock-rates =
			<320000000 0 0>,
			<404000000 0 0>,
			<480000000 0 0>,
			<600000000 0 0>;
		clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
		src-clock-name = "ife_clk_src";
		clock-names-option =  "ife_dsp_clk";
		clocks-option = <&camcc CAM_CC_IFE_0_DSP_CLK>;
		clock-rates-option = <600000000>;
		status = "ok";
	};

	cam_csid1: qcom,csid1@acba000 {
		cell-index = <1>;
		compatible = "qcom,csid170_200";
		reg-names = "csid";
		reg = <0xacba000 0x1000>;
		reg-cam-base = <0xba000>;
		interrupt-names = "csid";
		interrupts = <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>;
		regulator-names = "camss", "ife1";
		camss-supply = <&cam_cc_titan_top_gdsc>;
		ife1-supply = <&cam_cc_ife_1_gdsc>;
		clock-names =
			"ife_csid_clk_src",
			"ife_csid_clk",
			"cphy_rx_clk_src",
			"ife_cphy_rx_clk",
			"ife_clk_src",
			"ife_clk",
			"ife_axi_clk";
		clocks =
			<&camcc CAM_CC_IFE_1_CSID_CLK_SRC>,
			<&camcc CAM_CC_IFE_1_CSID_CLK>,
			<&camcc CAM_CC_CPHY_RX_CLK_SRC>,
			<&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
			<&camcc CAM_CC_IFE_1_CLK_SRC>,
			<&camcc CAM_CC_IFE_1_CLK>,
			<&camcc CAM_CC_IFE_1_AXI_CLK>;
		clock-rates =
			<300000000 0 0 0 320000000 0 0>,
			<384000000 0 0 0 404000000 0 0>,
			<400000000 0 0 0 480000000 0 0>,
			<400000000 0 0 0 600000000 0 0>;
		clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
		src-clock-name = "ife_csid_clk_src";
		status = "ok";
	};

	cam_vfe1: qcom,vfe1@acb6000 {
		cell-index = <1>;
		compatible = "qcom,vfe170_150";
		reg-names = "ife";
		reg = <0xacb6000 0x4000>;
		reg-cam-base = <0xb6000>;
		interrupt-names = "ife";
		interrupts = <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>;
		regulator-names = "camss", "ife1";
		camss-supply = <&cam_cc_titan_top_gdsc>;
		ife1-supply = <&cam_cc_ife_1_gdsc>;
		clock-names =
			"ife_clk_src",
			"ife_clk",
			"ife_axi_clk";
		clocks =
			<&camcc CAM_CC_IFE_1_CLK_SRC>,
			<&camcc CAM_CC_IFE_1_CLK>,
			<&camcc CAM_CC_IFE_1_AXI_CLK>;
		clock-rates =
			<320000000 0 0>,
			<404000000 0 0>,
			<480000000 0 0>,
			<600000000 0 0>;
		clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
		src-clock-name = "ife_clk_src";
		clock-names-option =  "ife_dsp_clk";
		clocks-option = <&camcc CAM_CC_IFE_1_DSP_CLK>;
		clock-rates-option = <600000000>;
		status = "ok";
	};

	cam_csid2: qcom,csid2@acc1000 {
		cell-index = <2>;
		compatible = "qcom,csid170_200";
		reg-names = "csid";
		reg = <0xacc1000 0x1000>;
		reg-cam-base = <0xc1000>;
		interrupt-names = "csid";
		interrupts = <GIC_SPI 718 IRQ_TYPE_EDGE_RISING>;
		regulator-names = "camss", "ife2";
		camss-supply = <&cam_cc_titan_top_gdsc>;
		ife2-supply = <&cam_cc_ife_2_gdsc>;
		clock-names =
			"ife_csid_clk_src",
			"ife_csid_clk",
			"cphy_rx_clk_src",
			"ife_cphy_rx_clk",
			"ife_clk_src",
			"ife_clk",
			"ife_axi_clk";
		clocks =
			<&camcc CAM_CC_IFE_2_CSID_CLK_SRC>,
			<&camcc CAM_CC_IFE_2_CSID_CLK>,
			<&camcc CAM_CC_CPHY_RX_CLK_SRC>,
			<&camcc CAM_CC_IFE_2_CPHY_RX_CLK>,
			<&camcc CAM_CC_IFE_2_CLK_SRC>,
			<&camcc CAM_CC_IFE_2_CLK>,
			<&camcc CAM_CC_IFE_2_AXI_CLK>;
		clock-rates =
			<300000000 0 0 0 320000000 0 0>,
			<384000000 0 0 0 404000000 0 0>,
			<400000000 0 0 0 480000000 0 0>,
			<400000000 0 0 0 600000000 0 0>;
		clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
		src-clock-name = "ife_csid_clk_src";
		status = "ok";
	};

	cam_vfe2: qcom,vfe2@acbd000 {
		cell-index = <2>;
		compatible = "qcom,vfe170_150";
		reg-names = "ife";
		reg = <0xacbd000 0x4000>;
		reg-cam-base = <0xbd000>;
		interrupt-names = "ife";
		interrupts = <GIC_SPI 719 IRQ_TYPE_EDGE_RISING>;
		regulator-names = "camss", "ife2";
		camss-supply = <&cam_cc_titan_top_gdsc>;
		ife2-supply = <&cam_cc_ife_2_gdsc>;
		clock-names =
			"ife_clk_src",
			"ife_clk",
			"ife_axi_clk";
		clocks =
			<&camcc CAM_CC_IFE_2_CLK_SRC>,
			<&camcc CAM_CC_IFE_2_CLK>,
			<&camcc CAM_CC_IFE_2_AXI_CLK>;
		clock-rates =
			<320000000 0 0>,
			<404000000 0 0>,
			<480000000 0 0>,
			<600000000 0 0>;
		clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
		src-clock-name = "ife_clk_src";
		clock-names-option =  "ife_dsp_clk";
		clocks-option = <&camcc CAM_CC_IFE_2_DSP_CLK>;
		clock-rates-option = <600000000>;
		status = "ok";
	};

	cam_csid_lite: qcom,csid-lite@acc8000 {
		cell-index = <3>;
		compatible = "qcom,csid-lite170";
		reg-names = "csid-lite";
		reg = <0xacc8000 0x1000>;
		reg-cam-base = <0xc8000>;
		interrupt-names = "csid-lite";
		interrupts = <GIC_SPI 473 IRQ_TYPE_EDGE_RISING>;
		regulator-names = "camss";
		camss-supply = <&cam_cc_titan_top_gdsc>;
		clock-names =
			"ife_csid_clk_src",
			"ife_csid_clk",
			"cphy_rx_clk_src",
			"ife_cphy_rx_clk",
			"ife_clk_src",
			"ife_clk";
		clocks =
			<&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
			<&camcc CAM_CC_IFE_LITE_CSID_CLK>,
			<&camcc CAM_CC_CPHY_RX_CLK_SRC>,
			<&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
			<&camcc CAM_CC_IFE_LITE_CLK_SRC>,
			<&camcc CAM_CC_IFE_LITE_CLK>;
		clock-rates =
			<300000000 0 0 0 320000000 0>,
			<384000000 0 0 0 400000000 0>,
			<400000000 0 0 0 480000000 0>,
			<400000000 0 0 0 600000000 0>;
		clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
		src-clock-name = "ife_csid_clk_src";
		status = "ok";
	};

	cam_vfe_lite: qcom,vfe-lite@acc4000 {
		cell-index = <3>;
		compatible = "qcom,vfe-lite170";
		reg-names = "ife-lite";
		reg = <0xacc4000 0x4000>;
		reg-cam-base = <0xc4000>;
		interrupt-names = "ife-lite";
		interrupts = <GIC_SPI 472 IRQ_TYPE_EDGE_RISING>;
		regulator-names = "camss";
		camss-supply = <&cam_cc_titan_top_gdsc>;
		clock-names =
			"ife_clk_src",
			"ife_clk";
		clocks =
			<&camcc CAM_CC_IFE_LITE_CLK_SRC>,
			<&camcc CAM_CC_IFE_LITE_CLK>;
		clock-rates =
			<320000000 0>,
			<400000000 0>,
			<480000000 0>,
			<600000000 0>;
		clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
		src-clock-name = "ife_clk_src";
		status = "ok";
	};

	qcom,cam-icp {
		compatible = "qcom,cam-icp";
		compat-hw-name = "qcom,a5",
			"qcom,ipe0",
			"qcom,bps";
		num-a5 = <1>;
		num-ipe = <1>;
		num-bps = <1>;
		status = "ok";
	};

	cam_a5: qcom,a5@ac00000 {
		cell-index = <0>;
		compatible = "qcom,cam-a5";
		reg = <0xac00000 0x6000>,
			<0xac10000 0x8000>,
			<0xac18000 0x3000>;
		reg-names = "a5_qgic", "a5_sierra", "a5_csr";
		reg-cam-base = <0x00000 0x10000 0x18000>;
		interrupts = <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>;
		interrupt-names = "a5";
		regulator-names = "camss-vdd";
		camss-vdd-supply = <&cam_cc_titan_top_gdsc>;
		clock-names =
			"soc_fast_ahb",
			"soc_ahb_clk",
			"icp_clk",
			"icp_clk_src";
		clocks =
			<&camcc CAM_CC_FAST_AHB_CLK_SRC>,
			<&camcc CAM_CC_SOC_AHB_CLK>,
			<&camcc CAM_CC_ICP_CLK>,
			<&camcc CAM_CC_ICP_CLK_SRC>;

		clock-rates =
			<100000000 0 0 384000000>,
			<200000000 0 0 404000000>,
			<300000000 0 0 600000000>,
			<404000000 0 0 600000000>;
		clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
		fw_name = "CAMERA_ICP.elf";
		ubwc-cfg = <0x73 0x1CF>;
		status = "ok";
	};

	cam_ipe0: qcom,ipe0 {
		cell-index = <0>;
		compatible = "qcom,cam-ipe";
		reg = <0xac87000 0xa000>;
		reg-names = "ipe0_top";
		reg-cam-base = <0x87000>;
		regulator-names = "ipe0-vdd";
		ipe0-vdd-supply = <&cam_cc_ipe_0_gdsc>;
		clock-names =
			"ipe_0_ahb_clk",
			"ipe_0_areg_clk",
			"ipe_0_axi_clk",
			"ipe_0_clk",
			"ipe_0_clk_src";
		src-clock-name = "ipe_0_clk_src";
		clocks = <&camcc CAM_CC_IPE_0_AHB_CLK>,
			<&camcc CAM_CC_IPE_0_AREG_CLK>,
			<&camcc CAM_CC_IPE_0_AXI_CLK>,
			<&camcc CAM_CC_IPE_0_CLK>,
			<&camcc CAM_CC_IPE_0_CLK_SRC>;

		clock-rates =
			<0 0 0 0 240000000>,
			<0 0 0 0 320000000>,
			<0 0 0 0 404000000>,
			<0 0 0 0 538000000>,
			<0 0 0 0 600000000>;
		clock-cntl-level = "lowsvs", "svs",
			"svs_l1", "nominal", "turbo";
		status = "ok";
	};

	cam_bps: qcom,bps {
		cell-index = <0>;
		compatible = "qcom,cam-bps";
		reg = <0xac6f000 0x8000>;
		reg-names = "bps_top";
		reg-cam-base = <0x6f000>;
		regulator-names = "bps-vdd";
		bps-vdd-supply = <&cam_cc_bps_gdsc>;
		clock-names = "bps_ahb_clk",
			"bps_areg_clk",
			"bps_axi_clk",
			"bps_clk",
			"bps_clk_src";
		src-clock-name = "bps_clk_src";
		clocks =
			<&camcc CAM_CC_BPS_AHB_CLK>,
			<&camcc CAM_CC_BPS_AREG_CLK>,
			<&camcc CAM_CC_BPS_AXI_CLK>,
			<&camcc CAM_CC_BPS_CLK>,
			<&camcc CAM_CC_BPS_CLK_SRC>;

		clock-rates =
			<0 0 0 0 200000000>,
			<0 0 0 0 404000000>,
			<0 0 0 0 480000000>,
			<0 0 0 0 600000000>,
			<0 0 0 0 600000000>;
		clock-cntl-level = "lowsvs", "svs",
			"svs_l1", "nominal", "turbo";
		status = "ok";
	};

	qcom,cam-jpeg {
		compatible = "qcom,cam-jpeg";
		compat-hw-name = "qcom,jpegenc",
			"qcom,jpegdma";
		num-jpeg-enc = <1>;
		num-jpeg-dma = <1>;
		status = "ok";
	};

	cam_jpeg_enc: qcom,jpegenc@ac4e000 {
		cell-index = <0>;
		compatible = "qcom,cam_jpeg_enc";
		reg-names = "jpege_hw";
		reg = <0xac4e000 0x4000>;
		reg-cam-base = <0x4e000>;
		interrupt-names = "jpeg";
		interrupts = <GIC_SPI 474 IRQ_TYPE_EDGE_RISING>;
		regulator-names = "camss-vdd";
		camss-vdd-supply = <&cam_cc_titan_top_gdsc>;
		clock-names =
			"jpegenc_clk_src",
			"jpegenc_clk";
		clocks =
			<&camcc CAM_CC_JPEG_CLK_SRC>,
			<&camcc CAM_CC_JPEG_CLK>;

		clock-rates =
			<600000000 0>;
		src-clock-name = "jpegenc_clk_src";
		clock-cntl-level = "nominal";
		status = "ok";
	};

	cam_jpeg_dma: qcom,jpegdma@0xac52000 {
		cell-index = <0>;
		compatible = "qcom,cam_jpeg_dma";
		reg-names = "jpegdma_hw";
		reg = <0xac52000 0x4000>;
		reg-cam-base = <0x52000>;
		interrupt-names = "jpegdma";
		interrupts = <GIC_SPI 475 IRQ_TYPE_EDGE_RISING>;
		regulator-names = "camss-vdd";
		camss-vdd-supply = <&cam_cc_titan_top_gdsc>;
		clock-names =
			"jpegdma_clk_src",
			"jpegdma_clk";
		clocks =
			<&camcc CAM_CC_JPEG_CLK_SRC>,
			<&camcc CAM_CC_JPEG_CLK>;

		clock-rates =
			<600000000 0>;
		src-clock-name = "jpegdma_clk_src";
		clock-cntl-level = "nominal";
		status = "ok";
	};

	qcom,cam-lrme {
		compatible = "qcom,cam-lrme";
		arch-compat = "lrme";
		status = "ok";
	};

	cam_lrme: qcom,lrme@ac6b000 {
		cell-index = <0>;
		compatible = "qcom,lrme";
		reg-names = "lrme";
		reg = <0xac6b000 0xa00>;
		reg-cam-base = <0x6b000>;
		interrupt-names = "lrme";
		interrupts = <GIC_SPI 476 IRQ_TYPE_EDGE_RISING>;
		regulator-names = "camss";
		camss-supply = <&cam_cc_titan_top_gdsc>;
		clock-names =
			"lrme_clk_src",
			"lrme_clk";
		clocks =
			<&camcc CAM_CC_LRME_CLK_SRC>,
			<&camcc CAM_CC_LRME_CLK>;
		clock-rates =
			<200000000 0>,
			<269333333 0>,
			<323200000 0>,
			<404000000 0>,
			<404000000 0>;
		clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal",
			"turbo";
		src-clock-name = "lrme_clk_src";
		status = "ok";
	};
};