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Commit 8d2f24ca authored by Daniel Vetter's avatar Daniel Vetter
Browse files

drm/i915: scramble reset support for DP port CRC on vlv 



They've moved the DC balance reset bit around. Again I don't think we
need it, but better safe than sorry and maybe HDMI port CRC will prove
useful for checking infoframes or hdmi audio.

v2: Apply the suggestions from Damien's review.

Reviewed-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 84093603

drivers/gpu/drm/i915/i915_debugfs.c

+46 −0
Original line number Diff line number Diff line
@@ -2026,6 +2026,9 @@ static int vlv_pipe_crc_ctl_reg(struct drm_device *dev, 
				enum intel_pipe_crc_source *source,

				uint32_t *val)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	bool need_stable_symbols = false;



	if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {

		int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);

		if (ret)
@@ -2038,9 +2041,11 @@ static int vlv_pipe_crc_ctl_reg(struct drm_device *dev, 
		break;

	case INTEL_PIPE_CRC_SOURCE_DP_B:

		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;

		need_stable_symbols = true;

		break;

	case INTEL_PIPE_CRC_SOURCE_DP_C:

		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;

		need_stable_symbols = true;

		break;

	case INTEL_PIPE_CRC_SOURCE_NONE:

		*val = 0;
@@ -2049,6 +2054,29 @@ static int vlv_pipe_crc_ctl_reg(struct drm_device *dev, 
		return -EINVAL;

	}



	/*

	 * When the pipe CRC tap point is after the transcoders we need

	 * to tweak symbol-level features to produce a deterministic series of

	 * symbols for a given frame. We need to reset those features only once

	 * a frame (instead of every nth symbol):

	 *   - DC-balance: used to ensure a better clock recovery from the data

	 *     link (SDVO)

	 *   - DisplayPort scrambling: used for EMI reduction

	 */

	if (need_stable_symbols) {

		uint32_t tmp = I915_READ(PORT_DFT2_G4X);



		WARN_ON(!IS_G4X(dev));



		tmp |= DC_BALANCE_RESET_VLV;

		if (pipe == PIPE_A)

			tmp |= PIPE_A_SCRAMBLE_RESET;

		else

			tmp |= PIPE_B_SCRAMBLE_RESET;



		I915_WRITE(PORT_DFT2_G4X, tmp);

	}



	return 0;

}
@@ -2128,6 +2156,22 @@ static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev, 
	return 0;

}



static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,

					 enum pipe pipe)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	uint32_t tmp = I915_READ(PORT_DFT2_G4X);



	if (pipe == PIPE_A)

		tmp &= ~PIPE_A_SCRAMBLE_RESET;

	else

		tmp &= ~PIPE_B_SCRAMBLE_RESET;

	if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))

		tmp &= ~DC_BALANCE_RESET_VLV;

	I915_WRITE(PORT_DFT2_G4X, tmp);



}



static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,

					 enum pipe pipe)

{
@@ -2267,6 +2311,8 @@ static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe, 


		if (IS_G4X(dev))

			g4x_undo_pipe_scramble_reset(dev, pipe);

		else if (IS_VALLEYVIEW(dev))

			vlv_undo_pipe_scramble_reset(dev, pipe);

	}



	return 0;