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Commit 8d1bdc46 authored by Mike Tipton's avatar Mike Tipton
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dt-bindings: clock: Add USB FORCE_MEM_CORE_ON bindings 



Add clock bindings to control the USB FORCE_MEM_CORE_ON bits.

Change-Id: I406e98e1be5b4d6702636c3bfdf738ae9ff12198
Signed-off-by: default avatarMike Tipton <mdtipton@codeaurora.org>
parent bf4eaa44

include/dt-bindings/clock/qcom,gcc-lahaina.h

+28 −26
Original line number Diff line number Diff line
@@ -188,32 +188,34 @@ 
#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC				176

#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK			177

#define GCC_USB30_PRIM_MASTER_CLK				178

#define GCC_USB30_PRIM_MASTER_CLK_SRC				179

#define GCC_USB30_PRIM_MOCK_UTMI_CLK				180

#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC			181

#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC		182

#define GCC_USB30_PRIM_SLEEP_CLK				183

#define GCC_USB30_SEC_MASTER_CLK				184

#define GCC_USB30_SEC_MASTER_CLK_SRC				185

#define GCC_USB30_SEC_MOCK_UTMI_CLK				186

#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC				187

#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC			188

#define GCC_USB30_SEC_SLEEP_CLK					189

#define GCC_USB3_PRIM_PHY_AUX_CLK				190

#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC				191

#define GCC_USB3_PRIM_PHY_COM_AUX_CLK				192

#define GCC_USB3_PRIM_PHY_PIPE_CLK				193

#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC				194

#define GCC_USB3_SEC_CLKREF_EN					195

#define GCC_USB3_SEC_PHY_AUX_CLK				196

#define GCC_USB3_SEC_PHY_AUX_CLK_SRC				197

#define GCC_USB3_SEC_PHY_COM_AUX_CLK				198

#define GCC_USB3_SEC_PHY_PIPE_CLK				199

#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC				200

#define GCC_VIDEO_AHB_CLK					201

#define GCC_VIDEO_AXI0_CLK					202

#define GCC_VIDEO_AXI1_CLK					203

#define GCC_VIDEO_XO_CLK					204

#define GCC_USB30_PRIM_MASTER_CLK__FORCE_MEM_CORE_ON		179

#define GCC_USB30_PRIM_MASTER_CLK_SRC				180

#define GCC_USB30_PRIM_MOCK_UTMI_CLK				181

#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC			182

#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC		183

#define GCC_USB30_PRIM_SLEEP_CLK				184

#define GCC_USB30_SEC_MASTER_CLK				185

#define GCC_USB30_SEC_MASTER_CLK__FORCE_MEM_CORE_ON		186

#define GCC_USB30_SEC_MASTER_CLK_SRC				187

#define GCC_USB30_SEC_MOCK_UTMI_CLK				188

#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC				189

#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC			190

#define GCC_USB30_SEC_SLEEP_CLK					191

#define GCC_USB3_PRIM_PHY_AUX_CLK				192

#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC				193

#define GCC_USB3_PRIM_PHY_COM_AUX_CLK				194

#define GCC_USB3_PRIM_PHY_PIPE_CLK				195

#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC				196

#define GCC_USB3_SEC_CLKREF_EN					197

#define GCC_USB3_SEC_PHY_AUX_CLK				198

#define GCC_USB3_SEC_PHY_AUX_CLK_SRC				199

#define GCC_USB3_SEC_PHY_COM_AUX_CLK				200

#define GCC_USB3_SEC_PHY_PIPE_CLK				201

#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC				202

#define GCC_VIDEO_AHB_CLK					203

#define GCC_VIDEO_AXI0_CLK					204

#define GCC_VIDEO_AXI1_CLK					205

#define GCC_VIDEO_XO_CLK					206



/* GCC resets */

#define GCC_CAMERA_BCR						0