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Commit 8cca30a7 authored by Noa Osherovich's avatar Noa Osherovich Committed by Leon Romanovsky
Browse files

net/mlx5: Expose mlx5e_link_mode 



The mlx5e_link_mode enumeration will also be used in mlx5_ib for RoCE.
This patch moves the enumeration to the mlx5 driver port header file.

Signed-off-by: default avatarNoa Osherovich <noaos@mellanox.com>
Signed-off-by: default avatarEran Ben Elisha <eranbe@mellanox.com>
Signed-off-by: default avatarSaeed Mahameed <saeedm@mellanox.com>
Signed-off-by: default avatarLeon Romanovsky <leon@kernel.org>
parent 2e353b34

drivers/net/ethernet/mellanox/mlx5/core/en.h

+0 −34
Original line number Diff line number Diff line
@@ -651,40 +651,6 @@ struct mlx5e_priv { 
	void                      *ppriv;

};



enum mlx5e_link_mode {

	MLX5E_1000BASE_CX_SGMII	 = 0,

	MLX5E_1000BASE_KX	 = 1,

	MLX5E_10GBASE_CX4	 = 2,

	MLX5E_10GBASE_KX4	 = 3,

	MLX5E_10GBASE_KR	 = 4,

	MLX5E_20GBASE_KR2	 = 5,

	MLX5E_40GBASE_CR4	 = 6,

	MLX5E_40GBASE_KR4	 = 7,

	MLX5E_56GBASE_R4	 = 8,

	MLX5E_10GBASE_CR	 = 12,

	MLX5E_10GBASE_SR	 = 13,

	MLX5E_10GBASE_ER	 = 14,

	MLX5E_40GBASE_SR4	 = 15,

	MLX5E_40GBASE_LR4	 = 16,

	MLX5E_50GBASE_SR2	 = 18,

	MLX5E_100GBASE_CR4	 = 20,

	MLX5E_100GBASE_SR4	 = 21,

	MLX5E_100GBASE_KR4	 = 22,

	MLX5E_100GBASE_LR4	 = 23,

	MLX5E_100BASE_TX	 = 24,

	MLX5E_1000BASE_T	 = 25,

	MLX5E_10GBASE_T		 = 26,

	MLX5E_25GBASE_CR	 = 27,

	MLX5E_25GBASE_KR	 = 28,

	MLX5E_25GBASE_SR	 = 29,

	MLX5E_50GBASE_CR2	 = 30,

	MLX5E_50GBASE_KR2	 = 31,

	MLX5E_LINK_MODES_NUMBER,

};



#define MLX5E_PROT_MASK(link_mode) (1 << link_mode)





void mlx5e_build_ptys2ethtool_map(void);



void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw);

include/linux/mlx5/port.h

+33 −0
Original line number Diff line number Diff line
@@ -61,6 +61,39 @@ enum mlx5_an_status { 
#define MLX5_I2C_ADDR_HIGH		0x51

#define MLX5_EEPROM_PAGE_LENGTH		256



enum mlx5e_link_mode {

	MLX5E_1000BASE_CX_SGMII	 = 0,

	MLX5E_1000BASE_KX	 = 1,

	MLX5E_10GBASE_CX4	 = 2,

	MLX5E_10GBASE_KX4	 = 3,

	MLX5E_10GBASE_KR	 = 4,

	MLX5E_20GBASE_KR2	 = 5,

	MLX5E_40GBASE_CR4	 = 6,

	MLX5E_40GBASE_KR4	 = 7,

	MLX5E_56GBASE_R4	 = 8,

	MLX5E_10GBASE_CR	 = 12,

	MLX5E_10GBASE_SR	 = 13,

	MLX5E_10GBASE_ER	 = 14,

	MLX5E_40GBASE_SR4	 = 15,

	MLX5E_40GBASE_LR4	 = 16,

	MLX5E_50GBASE_SR2	 = 18,

	MLX5E_100GBASE_CR4	 = 20,

	MLX5E_100GBASE_SR4	 = 21,

	MLX5E_100GBASE_KR4	 = 22,

	MLX5E_100GBASE_LR4	 = 23,

	MLX5E_100BASE_TX	 = 24,

	MLX5E_1000BASE_T	 = 25,

	MLX5E_10GBASE_T		 = 26,

	MLX5E_25GBASE_CR	 = 27,

	MLX5E_25GBASE_KR	 = 28,

	MLX5E_25GBASE_SR	 = 29,

	MLX5E_50GBASE_CR2	 = 30,

	MLX5E_50GBASE_KR2	 = 31,

	MLX5E_LINK_MODES_NUMBER,

};



#define MLX5E_PROT_MASK(link_mode) (1 << link_mode)



int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps);

int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys,

			 int ptys_size, int proto_mask, u8 local_port);