Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 8cc3fb5e authored by Anuj Garg's avatar Anuj Garg Committed by Gerrit - the friendly Code Review server
Browse files

ARM: dts: msm: Add device nodes for FastRPC and CDSP Loader for SA8195

Add fastrpc device tree nodes for CDSP, ADSP and SDSP for sa8195.
Add cdsp loader device tree node for sa8195.

Change-Id: Iac2cb70ceebceedd6adaea2efa41794c6034c350
parent eedf5958
Loading
Loading
Loading
Loading
+39 −0
Original line number Diff line number Diff line
@@ -154,6 +154,45 @@
		"kgsl_gmu_pdc_seq";
};

&msm_fastrpc {
	qcom,msm_fastrpc_compute_cb1 {
		iommus = <&apps_smmu 0x1001 0x0460>;
	};

	qcom,msm_fastrpc_compute_cb2 {
		iommus = <&apps_smmu 0x1002 0x0460>;
	};

	qcom,msm_fastrpc_compute_cb3 {
		iommus = <&apps_smmu 0x1003 0x0460>;
	};

	qcom,msm_fastrpc_compute_cb4 {
		iommus = <&apps_smmu 0x1004 0x0460>;
	};

	qcom,msm_fastrpc_compute_cb5 {
		iommus = <&apps_smmu 0x1005 0x0460>;
	};

	qcom,msm_fastrpc_compute_cb6 {
		iommus = <&apps_smmu 0x1006 0x0460>;
	};

	qcom,msm_fastrpc_compute_cb7 {
		iommus = <&apps_smmu 0x1007 0x0460>;
	};

	qcom,msm_fastrpc_compute_cb8 {
		iommus = <&apps_smmu 0x1008 0x0460>;
	};

	qcom,msm_fastrpc_compute_cb9 {
		iommus = <&apps_smmu 0x1009 0x0460>;
	};
};


&msm_vidc {
	qcom,allowed-clock-rates = <240000000 338000000
		365000000 444000000 533000000>;
+162 −0
Original line number Diff line number Diff line
@@ -1919,6 +1919,168 @@
		compatible = "qcom,tee-shared-memory-bridge";
	};

	qcom,msm-cdsp-loader {
		compatible = "qcom,cdsp-loader";
		qcom,proc-img-to-load = "cdsp";
	};

	qcom,msm-adsprpc-mem {
		compatible = "qcom,msm-adsprpc-mem-region";
		memory-region = <&adsp_mem>;
	};

	msm_fastrpc: qcom,msm_fastrpc {
		compatible = "qcom,msm-fastrpc-compute";
		qcom,fastrpc-adsp-audio-pdr;
		qcom,rpc-latency-us = <235>;
		qcom,adsp-remoteheap-vmid = <3 5 6>;

		qcom,msm_fastrpc_compute_cb1 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x1401 0x2040>,
				 <&apps_smmu 0x1421 0x0>,
				 <&apps_smmu 0x2001 0x420>,
				 <&apps_smmu 0x2041 0x0>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable";
			dma-coherent-hint-cached;
		};

		qcom,msm_fastrpc_compute_cb4 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x4 0x3440>,
				 <&apps_smmu 0x24 0x3400>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable";
			dma-coherent-hint-cached;
		};

		qcom,msm_fastrpc_compute_cb5 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x5 0x3440>,
				 <&apps_smmu 0x25 0x3400>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable";
			dma-coherent-hint-cached;
		};

		qcom,msm_fastrpc_compute_cb6 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x6 0x3460>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable";
			dma-coherent-hint-cached;
		};

		qcom,msm_fastrpc_compute_cb7 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x7 0x3460>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable";
			dma-coherent-hint-cached;
		};

		qcom,msm_fastrpc_compute_cb8 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x8 0x3460>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable";
			dma-coherent-hint-cached;
		};

		qcom,msm_fastrpc_compute_cb2 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x2 0x3440>,
				 <&apps_smmu 0x22 0x3400>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable";
			dma-coherent-hint-cached;
		};

		qcom,msm_fastrpc_compute_cb3 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x3 0x3440>,
				 <&apps_smmu 0x1423 0x0>,
				 <&apps_smmu 0x2023 0x0>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable";
			dma-coherent-hint-cached;
		};

		qcom,msm_fastrpc_compute_cb9 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			qcom,secure-context-bank;
			iommus = <&apps_smmu 0x9 0x3460>;
			qcom,iommu-dma-addr-pool = <0x60000000 0x78000000>;
			qcom,iommu-faults = "stall-disable";
			dma-coherent-hint-cached;
		};

		qcom,msm_fastrpc_compute_cb10 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "adsprpc-smd";
			iommus = <&apps_smmu 0x1b23 0x0>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable";
			dma-coherent-hint-cached;
		};

		qcom,msm_fastrpc_compute_cb11 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "adsprpc-smd";
			iommus = <&apps_smmu 0x1b24 0x0>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable";
			dma-coherent-hint-cached;
		};

		qcom,msm_fastrpc_compute_cb12 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "adsprpc-smd";
			iommus = <&apps_smmu 0x1b25 0x0>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable";
			dma-coherent-hint-cached;
		};

		qcom,msm_fastrpc_compute_cb13 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "sdsprpc-smd";
			iommus = <&apps_smmu 0x5a1 0x0>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable";
			dma-coherent-hint-cached;
		};

		qcom,msm_fastrpc_compute_cb14 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "sdsprpc-smd";
			iommus = <&apps_smmu 0x5a2 0x0>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable";
			dma-coherent-hint-cached;
		};

		qcom,msm_fastrpc_compute_cb15 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "sdsprpc-smd";
			iommus = <&apps_smmu 0x5a3 0x0>;
			shared-cb = <4>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable";
			dma-coherent-hint-cached;
		};
	};

	qcom_qseecom: qseecom@87900000 {
		compatible = "qcom,qseecom";
		reg = <0x87900000 0x2200000>;