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Commit 8c7bea32 authored by Emil Tantilov's avatar Emil Tantilov Committed by Jeff Kirsher
Browse files

ixgbe: Numerous whitespace / formatting cleanups 



This patch contains a number of whitespace and formatting cleanups.

Signed-off-by: default avatarEmil Tantilov <emil.s.tantilov@intel.com>
Tested-by: default avatarStephen Ko <stephen.s.ko@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent 63d778df

drivers/net/ixgbe/ixgbe_82598.c

+2 −5
Original line number Diff line number Diff line
@@ -627,7 +627,6 @@ static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, 
	return 0;

}





/**

 *  ixgbe_setup_mac_link_82598 - Set MAC link speed

 *  @hw: pointer to hardware structure
@@ -698,7 +697,6 @@ static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw, 
	/* Setup the PHY according to input speed */

	status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,

	                                      autoneg_wait_to_complete);



	/* Set up MAC */

	ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete);
@@ -1013,13 +1011,12 @@ static s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val) 
}



/**

 *  ixgbe_read_i2c_eeprom_82598 - Read 8 bit EEPROM word of an SFP+ module

 *  over I2C interface through an intermediate phy.

 *  ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface.

 *  @hw: pointer to hardware structure

 *  @byte_offset: EEPROM byte offset to read

 *  @eeprom_data: value read

 *

 *  Performs byte read operation to SFP module's EEPROM over I2C interface.

 *  Performs 8 byte read operation to SFP module's EEPROM over I2C interface.

 **/

static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,

				       u8 *eeprom_data)

drivers/net/ixgbe/ixgbe_82599.c

+9 −10
Original line number Diff line number Diff line
@@ -542,7 +542,6 @@ s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, 
		 * Section 73.10.2, we may have to wait up to 500ms if KR is

		 * attempted.  82599 uses the same timing for 10g SFI.

		 */



		for (i = 0; i < 5; i++) {

			/* Wait for the link partner to also set speed */

			msleep(100);
@@ -767,7 +766,6 @@ static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, 
	else

		orig_autoc = autoc;





	if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||

	    link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||

	    link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
@@ -1926,6 +1924,7 @@ static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval) 
		if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)

			break;

		else

			/* Use interrupt-safe sleep just in case */

			udelay(10);

	}

drivers/net/ixgbe/ixgbe_common.c

+4 −3
Original line number Diff line number Diff line
@@ -1555,7 +1555,9 @@ s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packetbuf_num) 
	 * 2: Tx flow control is enabled (we can send pause frames but

	 *    we do not support receiving pause frames).

	 * 3: Both Rx and Tx flow control (symmetric) are enabled.

#ifdef CONFIG_DCB

	 * 4: Priority Flow Control is enabled.

#endif

	 * other: Invalid.

	 */

	switch (hw->fc.current_mode) {
@@ -2392,7 +2394,6 @@ s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw) 
{

	int i;





	for (i = 0; i < 128; i++)

		IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);