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Commit 8c358435 authored by Suravee Suthikulpanit's avatar Suravee Suthikulpanit Committed by Greg Kroah-Hartman
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iommu/amd: Only support x2APIC with IVHD type 11h/40h 



[ Upstream commit 966b753cf3969553ca50bacd2b8c4ddade5ecc9e ]

Current implementation for IOMMU x2APIC support makes use of
the MMIO access to MSI capability block registers, which requires
checking EFR[MsiCapMmioSup]. However, only IVHD type 11h/40h contain
the information, and not in the IVHD type 10h IOMMU feature reporting
field. Since the BIOS in newer systems, which supports x2APIC, would
normally contain IVHD type 11h/40h, remove the IOMMU_FEAT_XTSUP_SHIFT
check for IVHD type 10h, and only support x2APIC with IVHD type 11h/40h.

Fixes: 66929812 ('iommu/amd: Add support for X2APIC IOMMU interrupts')
Signed-off-by: default avatarSuravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Signed-off-by: default avatarJoerg Roedel <jroedel@suse.de>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent b1b7add9

drivers/iommu/amd_iommu_init.c

+0 −2
Original line number Diff line number Diff line
@@ -1523,8 +1523,6 @@ static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h) 
			iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET;

		if (((h->efr_attr & (0x1 << IOMMU_FEAT_GASUP_SHIFT)) == 0))

			amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;

		if (((h->efr_attr & (0x1 << IOMMU_FEAT_XTSUP_SHIFT)) == 0))

			amd_iommu_xt_mode = IRQ_REMAP_XAPIC_MODE;

		break;

	case 0x11:

	case 0x40:

drivers/iommu/amd_iommu_types.h

+0 −1
Original line number Diff line number Diff line
@@ -377,7 +377,6 @@ 
#define IOMMU_CAP_EFR     27



/* IOMMU Feature Reporting Field (for IVHD type 10h */

#define IOMMU_FEAT_XTSUP_SHIFT	0

#define IOMMU_FEAT_GASUP_SHIFT	6



/* IOMMU Extended Feature Register (EFR) */