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Commit 8bb2f532 authored by Kunihiko Hayashi's avatar Kunihiko Hayashi Committed by Masahiro Yamada
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ARM: dts: uniphier: Add USB2 PHY nodes 



Add nodes of USB2 physical layer for UniPhier SoC. This supports Pro4.

Signed-off-by: default avatarKunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
parent 45be1573

arch/arm/boot/dts/uniphier-pro4.dtsi

+34 −1
Original line number Diff line number Diff line
@@ -328,6 +328,8 @@ 
				 <&mio_clk 12>;

			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,

				 <&mio_rst 12>;

			phy-names = "usb";

			phys = <&usb_phy0>;

			has-transaction-translator;

		};
@@ -342,6 +344,8 @@ 
				 <&mio_clk 13>;

			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,

				 <&mio_rst 13>;

			phy-names = "usb";

			phys = <&usb_phy1>;

			has-transaction-translator;

		};
@@ -353,6 +357,34 @@ 
			pinctrl: pinctrl {

				compatible = "socionext,uniphier-pro4-pinctrl";

			};



			usb-phy {

				compatible = "socionext,uniphier-pro4-usb2-phy";

				#address-cells = <1>;

				#size-cells = <0>;



				usb_phy0: phy@0 {

					reg = <0>;

					#phy-cells = <0>;

				};



				usb_phy1: phy@1 {

					reg = <1>;

					#phy-cells = <0>;

				};



				usb_phy2: phy@2 {

					reg = <2>;

					#phy-cells = <0>;

					vbus-supply = <&usb0_vbus>;

				};



				usb_phy3: phy@3 {

					reg = <3>;

					#phy-cells = <0>;

					vbus-supply = <&usb1_vbus>;

				};

			};

		};



		soc-glue@5f900000 {
@@ -456,7 +488,7 @@ 
			clock-names = "ref", "bus_early", "suspend";

			clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;

			resets = <&usb0_rst 4>;

			phys = <&usb0_ssphy>;

			phys = <&usb_phy2>, <&usb0_ssphy>;

			dr_mode = "host";

		};
@@ -509,6 +541,7 @@ 
			clock-names = "ref", "bus_early", "suspend";

			clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;

			resets = <&usb1_rst 4>;

			phys = <&usb_phy3>;

			dr_mode = "host";

		};