Loading drivers/clk/qcom/Kconfig +9 −0 Original line number Original line Diff line number Diff line Loading @@ -757,6 +757,15 @@ config SDW_GCC_MONACO Say Y if you want to use peripheral devices such as UART, SPI, I2C, Say Y if you want to use peripheral devices such as UART, SPI, I2C, USB, SD/eMMC, etc. USB, SD/eMMC, etc. config SDW_GPUCC_MONACO tristate "MONACO Graphics Clock Controller" select SDW_GCC_MONACO help Support for the graphics clock controller on Qualcomm Technologies, Inc. MONACO devices. Say Y if you want to support graphics controller devices and functionality such as 3D graphics. endif endif config VIRTIO_CLK config VIRTIO_CLK Loading drivers/clk/qcom/Makefile +1 −0 Original line number Original line Diff line number Diff line Loading @@ -72,6 +72,7 @@ obj-$(CONFIG_SDX_DEBUGCC_NIGHTJAR) += debugcc-sdxnightjar.o obj-$(CONFIG_SDX_GCC_LEMUR) += gcc-sdxlemur.o obj-$(CONFIG_SDX_GCC_LEMUR) += gcc-sdxlemur.o obj-$(CONFIG_SDX_GCC_NIGHTJAR) += gcc-sdxnightjar.o obj-$(CONFIG_SDX_GCC_NIGHTJAR) += gcc-sdxnightjar.o obj-$(CONFIG_SDW_GCC_MONACO) += gcc-monaco.o obj-$(CONFIG_SDW_GCC_MONACO) += gcc-monaco.o obj-$(CONFIG_SDW_GPUCC_MONACO) += gpucc-monaco.o obj-$(CONFIG_SM_CAMCC_6150) += camcc-sm6150.o obj-$(CONFIG_SM_CAMCC_6150) += camcc-sm6150.o obj-$(CONFIG_SM_CAMCC_8150) += camcc-sm8150.o obj-$(CONFIG_SM_CAMCC_8150) += camcc-sm8150.o obj-$(CONFIG_SM_CAMCC_SHIMA) += camcc-shima.o obj-$(CONFIG_SM_CAMCC_SHIMA) += camcc-shima.o Loading drivers/clk/qcom/gpucc-monaco.c 0 → 100644 +474 −0 Original line number Original line Diff line number Diff line // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2021, The Linux Foundation. All rights reserved. */ #include <linux/clk-provider.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/of_device.h> #include <linux/of.h> #include <linux/regmap.h> #include <dt-bindings/clock/qcom,gpucc-monaco.h> #include "clk-alpha-pll.h" #include "clk-branch.h" #include "clk-rcg.h" #include "clk-regmap-divider.h" #include "common.h" #include "vdd-level-monaco.h" static DEFINE_VDD_REGULATORS(vdd_cx, VDD_HIGH_L1 + 1, 1, vdd_corner); static struct clk_vdd_class *gpu_cc_monaco_regulators[] = { &vdd_cx, }; enum { P_BI_TCXO, P_GPLL0_OUT_MAIN, P_GPLL0_OUT_MAIN_DIV, P_GPU_CC_PLL0_OUT_EVEN, P_GPU_CC_PLL0_OUT_ODD, }; static struct pll_vco lucid_evo_vco[] = { { 249600000, 2000000000, 0 }, }; /* 310MHz configuration*/ static const struct alpha_pll_config gpu_cc_pll0_config = { .l = 0x10, .cal_l = 0x44, .alpha = 0x2555, .config_ctl_val = 0x20485699, .config_ctl_hi_val = 0x00182261, .config_ctl_hi1_val = 0x32AA299C, .user_ctl_val = 0x00000000, .user_ctl_hi_val = 0x00000805, }; static struct clk_alpha_pll gpu_cc_pll0 = { .offset = 0x0, .vco_table = lucid_evo_vco, .num_vco = ARRAY_SIZE(lucid_evo_vco), .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], .clkr = { .hw.init = &(struct clk_init_data){ .name = "gpu_cc_pll0", .parent_data = &(const struct clk_parent_data){ .fw_name = "bi_tcxo", }, .num_parents = 1, .ops = &clk_alpha_pll_lucid_evo_ops, }, .vdd_data = { .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER_D1] = 500000000, [VDD_LOWER] = 615000000, [VDD_LOW] = 1066000000, [VDD_LOW_L1] = 1500000000, [VDD_NOMINAL] = 1750000000, [VDD_HIGH] = 2000000000}, }, }, }; static const struct parent_map gpu_cc_parent_map_0[] = { { P_BI_TCXO, 0 }, }; static const struct clk_parent_data gpu_cc_parent_data_0_ao[] = { { .fw_name = "bi_tcxo_ao", }, }; static const struct parent_map gpu_cc_parent_map_1[] = { { P_BI_TCXO, 0 }, { P_GPU_CC_PLL0_OUT_EVEN, 1 }, { P_GPU_CC_PLL0_OUT_ODD, 2 }, { P_GPLL0_OUT_MAIN, 5 }, { P_GPLL0_OUT_MAIN_DIV, 6 }, }; static const struct clk_parent_data gpu_cc_parent_data_1[] = { { .fw_name = "bi_tcxo" }, { .hw = &gpu_cc_pll0.clkr.hw }, { .hw = &gpu_cc_pll0.clkr.hw }, { .fw_name = "gpll0_out_main" }, { .fw_name = "gpll0_out_main_div" }, }; static const struct parent_map gpu_cc_parent_map_2[] = { { P_BI_TCXO, 0 }, { P_GPU_CC_PLL0_OUT_EVEN, 1 }, { P_GPU_CC_PLL0_OUT_ODD, 2 }, { P_GPLL0_OUT_MAIN, 5 }, }; static const struct clk_parent_data gpu_cc_parent_data_2[] = { { .fw_name = "bi_tcxo" }, { .hw = &gpu_cc_pll0.clkr.hw }, { .hw = &gpu_cc_pll0.clkr.hw }, { .fw_name = "gpll0_out_main" }, }; static const struct freq_tbl ftbl_gpu_cc_cxo_aon_clk_src[] = { F(19200000, P_BI_TCXO, 1, 0, 0), { } }; static struct clk_rcg2 gpu_cc_cxo_aon_clk_src = { .cmd_rcgr = 0x4134, .mnd_width = 0, .hid_width = 5, .parent_map = gpu_cc_parent_map_0, .freq_tbl = ftbl_gpu_cc_cxo_aon_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "gpu_cc_cxo_aon_clk_src", .parent_data = gpu_cc_parent_data_0_ao, .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0_ao), .ops = &clk_rcg2_ops, }, }; static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), { } }; static struct clk_rcg2 gpu_cc_gmu_clk_src = { .cmd_rcgr = 0x4120, .mnd_width = 0, .hid_width = 5, .parent_map = gpu_cc_parent_map_1, .freq_tbl = ftbl_gpu_cc_gmu_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "gpu_cc_gmu_clk_src", .parent_data = gpu_cc_parent_data_1, .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1), .ops = &clk_rcg2_ops, }, .clkr.vdd_data = { .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 200000000}, }, }; static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src[] = { F(310000000, P_GPU_CC_PLL0_OUT_ODD, 1, 0, 0), F(470000000, P_GPU_CC_PLL0_OUT_ODD, 1, 0, 0), F(583000000, P_GPU_CC_PLL0_OUT_ODD, 1, 0, 0), F(700000000, P_GPU_CC_PLL0_OUT_ODD, 1, 0, 0), F(900000000, P_GPU_CC_PLL0_OUT_ODD, 1, 0, 0), F(1000000000, P_GPU_CC_PLL0_OUT_ODD, 1, 0, 0), { } }; static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src = { .cmd_rcgr = 0x4028, .mnd_width = 0, .hid_width = 5, .parent_map = gpu_cc_parent_map_2, .freq_tbl = ftbl_gpu_cc_gx_gfx3d_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "gpu_cc_gx_gfx3d_clk_src", .parent_data = gpu_cc_parent_data_2, .num_parents = ARRAY_SIZE(gpu_cc_parent_data_2), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, .clkr.vdd_data = { .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 310000000, [VDD_LOW] = 470000000, [VDD_LOW_L1] = 583000000, [VDD_NOMINAL] = 700000000, [VDD_HIGH] = 900000000, [VDD_HIGH_L1] = 1000000000}, }, }; static struct clk_branch gpu_cc_crc_ahb_clk = { .halt_reg = 0x407c, .halt_check = BRANCH_HALT_VOTED, .clkr = { .enable_reg = 0x407c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gpu_cc_crc_ahb_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gpu_cc_cx_apb_clk = { .halt_reg = 0x4088, .halt_check = BRANCH_HALT_VOTED, .clkr = { .enable_reg = 0x4088, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gpu_cc_cx_apb_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gpu_cc_cx_gfx3d_clk = { .halt_reg = 0x40a8, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x40a8, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gpu_cc_cx_gfx3d_clk", .parent_data = &(const struct clk_parent_data){ .hw = &gpu_cc_gx_gfx3d_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gpu_cc_cx_gfx3d_slv_clk = { .halt_reg = 0x40ac, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x40ac, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gpu_cc_cx_gfx3d_slv_clk", .parent_data = &(const struct clk_parent_data){ .hw = &gpu_cc_gx_gfx3d_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gpu_cc_cx_gmu_clk = { .halt_reg = 0x4098, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x4098, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gpu_cc_cx_gmu_clk", .parent_data = &(const struct clk_parent_data){ .hw = &gpu_cc_gmu_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gpu_cc_cx_snoc_dvm_clk = { .halt_reg = 0x408c, .halt_check = BRANCH_HALT_VOTED, .clkr = { .enable_reg = 0x408c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gpu_cc_cx_snoc_dvm_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gpu_cc_cxo_aon_clk = { .halt_reg = 0x414c, .halt_check = BRANCH_HALT_VOTED, .clkr = { .enable_reg = 0x414c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gpu_cc_cxo_aon_clk", .parent_data = &(const struct clk_parent_data){ .hw = &gpu_cc_cxo_aon_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gpu_cc_cxo_clk = { .halt_reg = 0x418c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x418c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gpu_cc_cxo_clk", .parent_data = &(const struct clk_parent_data){ .hw = &gpu_cc_cxo_aon_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gpu_cc_gx_cxo_clk = { .halt_reg = 0x416c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x416c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gpu_cc_gx_cxo_clk", .parent_data = &(const struct clk_parent_data){ .hw = &gpu_cc_cxo_aon_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gpu_cc_gx_gfx3d_clk = { .halt_reg = 0x404c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x404c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gpu_cc_gx_gfx3d_clk", .parent_data = &(const struct clk_parent_data){ .hw = &gpu_cc_gx_gfx3d_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gpu_cc_sleep_clk = { .halt_reg = 0x4090, .halt_check = BRANCH_HALT_VOTED, .clkr = { .enable_reg = 0x4090, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gpu_cc_sleep_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_regmap *gpu_cc_monaco_clocks[] = { [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr, [GPU_CC_CX_APB_CLK] = &gpu_cc_cx_apb_clk.clkr, [GPU_CC_CX_GFX3D_CLK] = &gpu_cc_cx_gfx3d_clk.clkr, [GPU_CC_CX_GFX3D_SLV_CLK] = &gpu_cc_cx_gfx3d_slv_clk.clkr, [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr, [GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr, [GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr, [GPU_CC_CXO_AON_CLK_SRC] = &gpu_cc_cxo_aon_clk_src.clkr, [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr, [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr, [GPU_CC_GX_CXO_CLK] = &gpu_cc_gx_cxo_clk.clkr, [GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr, [GPU_CC_GX_GFX3D_CLK_SRC] = &gpu_cc_gx_gfx3d_clk_src.clkr, [GPU_CC_PLL0] = &gpu_cc_pll0.clkr, [GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr, }; static const struct regmap_config gpu_cc_monaco_regmap_config = { .reg_bits = 32, .reg_stride = 4, .val_bits = 32, .max_register = 0x9008, .fast_io = true, }; static const struct qcom_cc_desc gpu_cc_monaco_desc = { .config = &gpu_cc_monaco_regmap_config, .clks = gpu_cc_monaco_clocks, .num_clks = ARRAY_SIZE(gpu_cc_monaco_clocks), .clk_regulators = gpu_cc_monaco_regulators, .num_clk_regulators = ARRAY_SIZE(gpu_cc_monaco_regulators), }; static const struct of_device_id gpu_cc_monaco_match_table[] = { { .compatible = "qcom,monaco-gpucc" }, { } }; MODULE_DEVICE_TABLE(of, gpu_cc_monaco_match_table); static int gpu_cc_monaco_probe(struct platform_device *pdev) { struct regmap *regmap; int ret; regmap = qcom_cc_map(pdev, &gpu_cc_monaco_desc); if (IS_ERR(regmap)) return PTR_ERR(regmap); clk_lucid_evo_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); /* Keep Always ON clocks * GPU_CC_AHB_CLK */ regmap_update_bits(regmap, 0x4078, BIT(0), BIT(0)); ret = qcom_cc_really_probe(pdev, &gpu_cc_monaco_desc, regmap); if (ret) { dev_err(&pdev->dev, "Failed to register GPU CC clocks\n"); return ret; } dev_info(&pdev->dev, "Registered GPU CC clocks\n"); return ret; } static void gpu_cc_monaco_sync_state(struct device *dev) { qcom_cc_sync_state(dev, &gpu_cc_monaco_desc); } static struct platform_driver gpu_cc_monaco_driver = { .probe = gpu_cc_monaco_probe, .driver = { .name = "gpu_cc-monaco", .of_match_table = gpu_cc_monaco_match_table, .sync_state = gpu_cc_monaco_sync_state, }, }; static int __init gpu_cc_monaco_init(void) { return platform_driver_register(&gpu_cc_monaco_driver); } subsys_initcall(gpu_cc_monaco_init); static void __exit gpu_cc_monaco_exit(void) { platform_driver_unregister(&gpu_cc_monaco_driver); } module_exit(gpu_cc_monaco_exit); MODULE_DESCRIPTION("QTI GPU_CC MONACO Driver"); MODULE_LICENSE("GPL v2"); drivers/clk/qcom/vdd-level-monaco.h +4 −2 Original line number Original line Diff line number Diff line /* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */ /* /* * Copyright (c) 2020, The Linux Foundation. All rights reserved. * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. */ */ #ifndef __DRIVERS_CLK_QCOM_VDD_LEVEL_H #ifndef __DRIVERS_CLK_QCOM_VDD_LEVEL_H Loading @@ -17,7 +17,8 @@ enum vdd_levels { VDD_LOW_L1, /* SVSL1 */ VDD_LOW_L1, /* SVSL1 */ VDD_NOMINAL, /* NOM */ VDD_NOMINAL, /* NOM */ VDD_NOMINAL_L1, /* NOM L1 */ VDD_NOMINAL_L1, /* NOM L1 */ VDD_HIGH, /* TURBO */ VDD_HIGH, VDD_HIGH_L1, /* TURBO L1*/ VDD_NUM, VDD_NUM, }; }; Loading @@ -30,6 +31,7 @@ static int vdd_corner[] = { [VDD_NOMINAL] = RPMH_REGULATOR_LEVEL_NOM, [VDD_NOMINAL] = RPMH_REGULATOR_LEVEL_NOM, [VDD_NOMINAL_L1] = RPMH_REGULATOR_LEVEL_NOM_L1, [VDD_NOMINAL_L1] = RPMH_REGULATOR_LEVEL_NOM_L1, [VDD_HIGH] = RPMH_REGULATOR_LEVEL_TURBO, [VDD_HIGH] = RPMH_REGULATOR_LEVEL_TURBO, [VDD_HIGH_L1] = RPMH_REGULATOR_LEVEL_TURBO_L1, }; }; #endif #endif Loading
drivers/clk/qcom/Kconfig +9 −0 Original line number Original line Diff line number Diff line Loading @@ -757,6 +757,15 @@ config SDW_GCC_MONACO Say Y if you want to use peripheral devices such as UART, SPI, I2C, Say Y if you want to use peripheral devices such as UART, SPI, I2C, USB, SD/eMMC, etc. USB, SD/eMMC, etc. config SDW_GPUCC_MONACO tristate "MONACO Graphics Clock Controller" select SDW_GCC_MONACO help Support for the graphics clock controller on Qualcomm Technologies, Inc. MONACO devices. Say Y if you want to support graphics controller devices and functionality such as 3D graphics. endif endif config VIRTIO_CLK config VIRTIO_CLK Loading
drivers/clk/qcom/Makefile +1 −0 Original line number Original line Diff line number Diff line Loading @@ -72,6 +72,7 @@ obj-$(CONFIG_SDX_DEBUGCC_NIGHTJAR) += debugcc-sdxnightjar.o obj-$(CONFIG_SDX_GCC_LEMUR) += gcc-sdxlemur.o obj-$(CONFIG_SDX_GCC_LEMUR) += gcc-sdxlemur.o obj-$(CONFIG_SDX_GCC_NIGHTJAR) += gcc-sdxnightjar.o obj-$(CONFIG_SDX_GCC_NIGHTJAR) += gcc-sdxnightjar.o obj-$(CONFIG_SDW_GCC_MONACO) += gcc-monaco.o obj-$(CONFIG_SDW_GCC_MONACO) += gcc-monaco.o obj-$(CONFIG_SDW_GPUCC_MONACO) += gpucc-monaco.o obj-$(CONFIG_SM_CAMCC_6150) += camcc-sm6150.o obj-$(CONFIG_SM_CAMCC_6150) += camcc-sm6150.o obj-$(CONFIG_SM_CAMCC_8150) += camcc-sm8150.o obj-$(CONFIG_SM_CAMCC_8150) += camcc-sm8150.o obj-$(CONFIG_SM_CAMCC_SHIMA) += camcc-shima.o obj-$(CONFIG_SM_CAMCC_SHIMA) += camcc-shima.o Loading
drivers/clk/qcom/gpucc-monaco.c 0 → 100644 +474 −0 Original line number Original line Diff line number Diff line // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2021, The Linux Foundation. All rights reserved. */ #include <linux/clk-provider.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/of_device.h> #include <linux/of.h> #include <linux/regmap.h> #include <dt-bindings/clock/qcom,gpucc-monaco.h> #include "clk-alpha-pll.h" #include "clk-branch.h" #include "clk-rcg.h" #include "clk-regmap-divider.h" #include "common.h" #include "vdd-level-monaco.h" static DEFINE_VDD_REGULATORS(vdd_cx, VDD_HIGH_L1 + 1, 1, vdd_corner); static struct clk_vdd_class *gpu_cc_monaco_regulators[] = { &vdd_cx, }; enum { P_BI_TCXO, P_GPLL0_OUT_MAIN, P_GPLL0_OUT_MAIN_DIV, P_GPU_CC_PLL0_OUT_EVEN, P_GPU_CC_PLL0_OUT_ODD, }; static struct pll_vco lucid_evo_vco[] = { { 249600000, 2000000000, 0 }, }; /* 310MHz configuration*/ static const struct alpha_pll_config gpu_cc_pll0_config = { .l = 0x10, .cal_l = 0x44, .alpha = 0x2555, .config_ctl_val = 0x20485699, .config_ctl_hi_val = 0x00182261, .config_ctl_hi1_val = 0x32AA299C, .user_ctl_val = 0x00000000, .user_ctl_hi_val = 0x00000805, }; static struct clk_alpha_pll gpu_cc_pll0 = { .offset = 0x0, .vco_table = lucid_evo_vco, .num_vco = ARRAY_SIZE(lucid_evo_vco), .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], .clkr = { .hw.init = &(struct clk_init_data){ .name = "gpu_cc_pll0", .parent_data = &(const struct clk_parent_data){ .fw_name = "bi_tcxo", }, .num_parents = 1, .ops = &clk_alpha_pll_lucid_evo_ops, }, .vdd_data = { .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER_D1] = 500000000, [VDD_LOWER] = 615000000, [VDD_LOW] = 1066000000, [VDD_LOW_L1] = 1500000000, [VDD_NOMINAL] = 1750000000, [VDD_HIGH] = 2000000000}, }, }, }; static const struct parent_map gpu_cc_parent_map_0[] = { { P_BI_TCXO, 0 }, }; static const struct clk_parent_data gpu_cc_parent_data_0_ao[] = { { .fw_name = "bi_tcxo_ao", }, }; static const struct parent_map gpu_cc_parent_map_1[] = { { P_BI_TCXO, 0 }, { P_GPU_CC_PLL0_OUT_EVEN, 1 }, { P_GPU_CC_PLL0_OUT_ODD, 2 }, { P_GPLL0_OUT_MAIN, 5 }, { P_GPLL0_OUT_MAIN_DIV, 6 }, }; static const struct clk_parent_data gpu_cc_parent_data_1[] = { { .fw_name = "bi_tcxo" }, { .hw = &gpu_cc_pll0.clkr.hw }, { .hw = &gpu_cc_pll0.clkr.hw }, { .fw_name = "gpll0_out_main" }, { .fw_name = "gpll0_out_main_div" }, }; static const struct parent_map gpu_cc_parent_map_2[] = { { P_BI_TCXO, 0 }, { P_GPU_CC_PLL0_OUT_EVEN, 1 }, { P_GPU_CC_PLL0_OUT_ODD, 2 }, { P_GPLL0_OUT_MAIN, 5 }, }; static const struct clk_parent_data gpu_cc_parent_data_2[] = { { .fw_name = "bi_tcxo" }, { .hw = &gpu_cc_pll0.clkr.hw }, { .hw = &gpu_cc_pll0.clkr.hw }, { .fw_name = "gpll0_out_main" }, }; static const struct freq_tbl ftbl_gpu_cc_cxo_aon_clk_src[] = { F(19200000, P_BI_TCXO, 1, 0, 0), { } }; static struct clk_rcg2 gpu_cc_cxo_aon_clk_src = { .cmd_rcgr = 0x4134, .mnd_width = 0, .hid_width = 5, .parent_map = gpu_cc_parent_map_0, .freq_tbl = ftbl_gpu_cc_cxo_aon_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "gpu_cc_cxo_aon_clk_src", .parent_data = gpu_cc_parent_data_0_ao, .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0_ao), .ops = &clk_rcg2_ops, }, }; static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), { } }; static struct clk_rcg2 gpu_cc_gmu_clk_src = { .cmd_rcgr = 0x4120, .mnd_width = 0, .hid_width = 5, .parent_map = gpu_cc_parent_map_1, .freq_tbl = ftbl_gpu_cc_gmu_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "gpu_cc_gmu_clk_src", .parent_data = gpu_cc_parent_data_1, .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1), .ops = &clk_rcg2_ops, }, .clkr.vdd_data = { .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 200000000}, }, }; static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src[] = { F(310000000, P_GPU_CC_PLL0_OUT_ODD, 1, 0, 0), F(470000000, P_GPU_CC_PLL0_OUT_ODD, 1, 0, 0), F(583000000, P_GPU_CC_PLL0_OUT_ODD, 1, 0, 0), F(700000000, P_GPU_CC_PLL0_OUT_ODD, 1, 0, 0), F(900000000, P_GPU_CC_PLL0_OUT_ODD, 1, 0, 0), F(1000000000, P_GPU_CC_PLL0_OUT_ODD, 1, 0, 0), { } }; static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src = { .cmd_rcgr = 0x4028, .mnd_width = 0, .hid_width = 5, .parent_map = gpu_cc_parent_map_2, .freq_tbl = ftbl_gpu_cc_gx_gfx3d_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "gpu_cc_gx_gfx3d_clk_src", .parent_data = gpu_cc_parent_data_2, .num_parents = ARRAY_SIZE(gpu_cc_parent_data_2), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, .clkr.vdd_data = { .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 310000000, [VDD_LOW] = 470000000, [VDD_LOW_L1] = 583000000, [VDD_NOMINAL] = 700000000, [VDD_HIGH] = 900000000, [VDD_HIGH_L1] = 1000000000}, }, }; static struct clk_branch gpu_cc_crc_ahb_clk = { .halt_reg = 0x407c, .halt_check = BRANCH_HALT_VOTED, .clkr = { .enable_reg = 0x407c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gpu_cc_crc_ahb_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gpu_cc_cx_apb_clk = { .halt_reg = 0x4088, .halt_check = BRANCH_HALT_VOTED, .clkr = { .enable_reg = 0x4088, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gpu_cc_cx_apb_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gpu_cc_cx_gfx3d_clk = { .halt_reg = 0x40a8, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x40a8, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gpu_cc_cx_gfx3d_clk", .parent_data = &(const struct clk_parent_data){ .hw = &gpu_cc_gx_gfx3d_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gpu_cc_cx_gfx3d_slv_clk = { .halt_reg = 0x40ac, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x40ac, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gpu_cc_cx_gfx3d_slv_clk", .parent_data = &(const struct clk_parent_data){ .hw = &gpu_cc_gx_gfx3d_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gpu_cc_cx_gmu_clk = { .halt_reg = 0x4098, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x4098, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gpu_cc_cx_gmu_clk", .parent_data = &(const struct clk_parent_data){ .hw = &gpu_cc_gmu_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gpu_cc_cx_snoc_dvm_clk = { .halt_reg = 0x408c, .halt_check = BRANCH_HALT_VOTED, .clkr = { .enable_reg = 0x408c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gpu_cc_cx_snoc_dvm_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gpu_cc_cxo_aon_clk = { .halt_reg = 0x414c, .halt_check = BRANCH_HALT_VOTED, .clkr = { .enable_reg = 0x414c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gpu_cc_cxo_aon_clk", .parent_data = &(const struct clk_parent_data){ .hw = &gpu_cc_cxo_aon_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gpu_cc_cxo_clk = { .halt_reg = 0x418c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x418c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gpu_cc_cxo_clk", .parent_data = &(const struct clk_parent_data){ .hw = &gpu_cc_cxo_aon_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gpu_cc_gx_cxo_clk = { .halt_reg = 0x416c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x416c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gpu_cc_gx_cxo_clk", .parent_data = &(const struct clk_parent_data){ .hw = &gpu_cc_cxo_aon_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gpu_cc_gx_gfx3d_clk = { .halt_reg = 0x404c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x404c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gpu_cc_gx_gfx3d_clk", .parent_data = &(const struct clk_parent_data){ .hw = &gpu_cc_gx_gfx3d_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gpu_cc_sleep_clk = { .halt_reg = 0x4090, .halt_check = BRANCH_HALT_VOTED, .clkr = { .enable_reg = 0x4090, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gpu_cc_sleep_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_regmap *gpu_cc_monaco_clocks[] = { [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr, [GPU_CC_CX_APB_CLK] = &gpu_cc_cx_apb_clk.clkr, [GPU_CC_CX_GFX3D_CLK] = &gpu_cc_cx_gfx3d_clk.clkr, [GPU_CC_CX_GFX3D_SLV_CLK] = &gpu_cc_cx_gfx3d_slv_clk.clkr, [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr, [GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr, [GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr, [GPU_CC_CXO_AON_CLK_SRC] = &gpu_cc_cxo_aon_clk_src.clkr, [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr, [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr, [GPU_CC_GX_CXO_CLK] = &gpu_cc_gx_cxo_clk.clkr, [GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr, [GPU_CC_GX_GFX3D_CLK_SRC] = &gpu_cc_gx_gfx3d_clk_src.clkr, [GPU_CC_PLL0] = &gpu_cc_pll0.clkr, [GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr, }; static const struct regmap_config gpu_cc_monaco_regmap_config = { .reg_bits = 32, .reg_stride = 4, .val_bits = 32, .max_register = 0x9008, .fast_io = true, }; static const struct qcom_cc_desc gpu_cc_monaco_desc = { .config = &gpu_cc_monaco_regmap_config, .clks = gpu_cc_monaco_clocks, .num_clks = ARRAY_SIZE(gpu_cc_monaco_clocks), .clk_regulators = gpu_cc_monaco_regulators, .num_clk_regulators = ARRAY_SIZE(gpu_cc_monaco_regulators), }; static const struct of_device_id gpu_cc_monaco_match_table[] = { { .compatible = "qcom,monaco-gpucc" }, { } }; MODULE_DEVICE_TABLE(of, gpu_cc_monaco_match_table); static int gpu_cc_monaco_probe(struct platform_device *pdev) { struct regmap *regmap; int ret; regmap = qcom_cc_map(pdev, &gpu_cc_monaco_desc); if (IS_ERR(regmap)) return PTR_ERR(regmap); clk_lucid_evo_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); /* Keep Always ON clocks * GPU_CC_AHB_CLK */ regmap_update_bits(regmap, 0x4078, BIT(0), BIT(0)); ret = qcom_cc_really_probe(pdev, &gpu_cc_monaco_desc, regmap); if (ret) { dev_err(&pdev->dev, "Failed to register GPU CC clocks\n"); return ret; } dev_info(&pdev->dev, "Registered GPU CC clocks\n"); return ret; } static void gpu_cc_monaco_sync_state(struct device *dev) { qcom_cc_sync_state(dev, &gpu_cc_monaco_desc); } static struct platform_driver gpu_cc_monaco_driver = { .probe = gpu_cc_monaco_probe, .driver = { .name = "gpu_cc-monaco", .of_match_table = gpu_cc_monaco_match_table, .sync_state = gpu_cc_monaco_sync_state, }, }; static int __init gpu_cc_monaco_init(void) { return platform_driver_register(&gpu_cc_monaco_driver); } subsys_initcall(gpu_cc_monaco_init); static void __exit gpu_cc_monaco_exit(void) { platform_driver_unregister(&gpu_cc_monaco_driver); } module_exit(gpu_cc_monaco_exit); MODULE_DESCRIPTION("QTI GPU_CC MONACO Driver"); MODULE_LICENSE("GPL v2");
drivers/clk/qcom/vdd-level-monaco.h +4 −2 Original line number Original line Diff line number Diff line /* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */ /* /* * Copyright (c) 2020, The Linux Foundation. All rights reserved. * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. */ */ #ifndef __DRIVERS_CLK_QCOM_VDD_LEVEL_H #ifndef __DRIVERS_CLK_QCOM_VDD_LEVEL_H Loading @@ -17,7 +17,8 @@ enum vdd_levels { VDD_LOW_L1, /* SVSL1 */ VDD_LOW_L1, /* SVSL1 */ VDD_NOMINAL, /* NOM */ VDD_NOMINAL, /* NOM */ VDD_NOMINAL_L1, /* NOM L1 */ VDD_NOMINAL_L1, /* NOM L1 */ VDD_HIGH, /* TURBO */ VDD_HIGH, VDD_HIGH_L1, /* TURBO L1*/ VDD_NUM, VDD_NUM, }; }; Loading @@ -30,6 +31,7 @@ static int vdd_corner[] = { [VDD_NOMINAL] = RPMH_REGULATOR_LEVEL_NOM, [VDD_NOMINAL] = RPMH_REGULATOR_LEVEL_NOM, [VDD_NOMINAL_L1] = RPMH_REGULATOR_LEVEL_NOM_L1, [VDD_NOMINAL_L1] = RPMH_REGULATOR_LEVEL_NOM_L1, [VDD_HIGH] = RPMH_REGULATOR_LEVEL_TURBO, [VDD_HIGH] = RPMH_REGULATOR_LEVEL_TURBO, [VDD_HIGH_L1] = RPMH_REGULATOR_LEVEL_TURBO_L1, }; }; #endif #endif
