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Commit 8b2608f1 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amd/display: update bw_calcs to take pipe sync into account (v3) 



Properly set all_displays_in_sync so that when the data is
propagated to powerplay, it's set properly and we can enable
mclk switching when all monitors are in sync.

v2: fix logic, clean up
v3: check for blending chains, simplify logic

Acked-by: default avatarEvan Quan <evan.quan@amd.com>
Reviewed-by: default avatarNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 55b85206

drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c

+28 −2
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ 


#include <linux/slab.h>



#include "resource.h"

#include "dm_services.h"

#include "dce_calcs.h"

#include "dc.h"
@@ -2977,6 +2978,32 @@ static void populate_initial_data( 
	data->number_of_displays = num_displays;

}



static bool all_displays_in_sync(const struct pipe_ctx pipe[],

				 int pipe_count)

{

	const struct pipe_ctx *active_pipes[MAX_PIPES];

	int i, num_active_pipes = 0;



	for (i = 0; i < pipe_count; i++) {

		if (!pipe[i].stream || pipe[i].top_pipe)

			continue;



		active_pipes[num_active_pipes++] = &pipe[i];

	}



	if (!num_active_pipes)

		return false;



	for (i = 1; i < num_active_pipes; ++i) {

		if (!resource_are_streams_timing_synchronizable(

			    active_pipes[0]->stream, active_pipes[i]->stream)) {

			return false;

		}

	}



	return true;

}



/**

 * Return:

 *	true -	Display(s) configuration supported.
@@ -2998,8 +3025,7 @@ bool bw_calcs(struct dc_context *ctx, 


	populate_initial_data(pipe, pipe_count, data);



	/*TODO: this should be taken out calcs output and assigned during timing sync for pplib use*/

	calcs_output->all_displays_in_sync = false;

	calcs_output->all_displays_in_sync = all_displays_in_sync(pipe, pipe_count);



	if (data->number_of_displays != 0) {

		uint8_t yclk_lvl, sclk_lvl;