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Commit 8b19c813 authored by Charles Keepax's avatar Charles Keepax Committed by Greg Kroah-Hartman
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ASoC: wm8974: Correct PLL rate rounding 



[ Upstream commit 9b17d3724df55ecc2bc67978822585f2b023be48 ]

Using a single value of 22500000 for both 48000Hz and 44100Hz audio
will sometimes result in returning wrong dividers due to rounding.
Update the code to use the actual value for both.

Fixes: 51b2bb3f ("ASoC: wm8974: configure pll and mclk divider automatically")
Signed-off-by: default avatarCharles Keepax <ckeepax@opensource.cirrus.com>
Link: https://patch.msgid.link/20250821082639.1301453-4-ckeepax@opensource.cirrus.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent cbeccd02

sound/soc/codecs/wm8974.c

+6 −2
Original line number Diff line number Diff line
@@ -427,10 +427,14 @@ static int wm8974_update_clocks(struct snd_soc_dai *dai) 
	fs256 = 256 * priv->fs;



	f = wm8974_get_mclkdiv(priv->mclk, fs256, &mclkdiv);



	if (f != priv->mclk) {

		/* The PLL performs best around 90MHz */

		fpll = wm8974_get_mclkdiv(22500000, fs256, &mclkdiv);

		if (fs256 % 8000)

			f = 22579200;

		else

			f = 24576000;



		fpll = wm8974_get_mclkdiv(f, fs256, &mclkdiv);

	}



	wm8974_set_dai_pll(dai, 0, 0, priv->mclk, fpll);