Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 8b114acf authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "dt-bindings: arm: msm: add entry for number of PARF testbus selectors"

parents 585e36f5 d97d709d
Loading
Loading
Loading
Loading
+7 −0
Original line number Diff line number Diff line
@@ -351,6 +351,12 @@ interconnects:
		de-asserted. This guarantees the 100MHz clock is available for
		the PCIe devices

- qcom,num-parf-testbus-sel:
	Usage: optional
	Value type: <u32>
	Definition: Defines the number of testbus selectors available for PARF
		for a given PCIe controller.

- qcom,switch-latency:
	Usage: optional
	Definition: The latency(ms) between when PCIe link is up and before
@@ -553,6 +559,7 @@ Example
		qcom,perst-delay-us-min = <10>;
		qcom,perst-delay-us-max = <15>;
		qcom,ep-latency = <20>;
		qcom,num-parf-testbus-sel = <0xb9>;
		qcom,switch-latency = <25>;

		qcom,eq-pset-req-vec = <0>;
+2 −0
Original line number Diff line number Diff line
@@ -117,6 +117,7 @@
		qcom,l1-2-th-value = <70>;
		qcom,slv-addr-space-size = <0x4000000>;
		qcom,ep-latency = <10>;
		qcom,num-parf-testbus-sel = <0xb9>;

		qcom,pcie-phy-ver = <10100>;
		qcom,phy-status-offset = <0x214>;
@@ -351,6 +352,7 @@
		qcom,no-l0s-supported;
		qcom,slv-addr-space-size = <0x20000000>;
		qcom,ep-latency = <10>;
		qcom,num-parf-testbus-sel = <0xb9>;

		qcom,pcie-phy-ver = <1106>;
		qcom,phy-status-offset = <0x214>;
+1 −0
Original line number Diff line number Diff line
@@ -110,6 +110,7 @@
		qcom,eq-fmdc-t-min-phase23 = <1>;
		qcom,slv-addr-space-size = <0x40000000>;
		qcom,ep-latency = <10>;
		qcom,num-parf-testbus-sel = <0xb9>;

		qcom,pcie-phy-ver = <1102>;
		qcom,phy-status-offset = <0x1214>;
+1 −0
Original line number Diff line number Diff line
@@ -113,6 +113,7 @@
		qcom,l1-2-th-value = <70>;
		qcom,slv-addr-space-size = <0x4000000>;
		qcom,ep-latency = <10>;
		qcom,num-parf-testbus-sel = <0xb9>;

		qcom,phy-manage-pll = <1>;
		qcom,phy-resetsm-cntrl2 = <0xa0>;