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Commit 8a9365a4 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'x86-cpufeature-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 cpufeature updates from Ingo Molnar:
 "The main changes in this cycle were related to enable ring-3
  MONITOR/MWAIT instructions support on supported CPUs, by Grzegorz
  Andrejczuk and Piotr Luc"

* 'x86-cpufeature-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/cpufeature: Move RING3MWAIT feature to avoid conflicts
  x86/cpufeature: Enable RING3MWAIT for Knights Mill
  x86/cpufeature: Enable RING3MWAIT for Knights Landing
  x86/cpufeature: Add RING3MWAIT to CPU features
  x86/elf: Add HWCAP2 to expose ring 3 MONITOR/MWAIT
  x86/msr: Add MSR_MISC_FEATURE_ENABLES and RING3MWAIT bit
  x86/cpufeature: Add AVX512_VPOPCNTDQ feature
parents 2891e8e6 3bba73b1

Documentation/admin-guide/kernel-parameters.txt

+4 −0
Original line number Original line Diff line number Diff line
@@ -3561,6 +3561,10 @@ 
	rhash_entries=	[KNL,NET]

	rhash_entries=	[KNL,NET]

			Set number of hash buckets for route cache

			Set number of hash buckets for route cache





	ring3mwait=disable

			[KNL] Disable ring 3 MONITOR/MWAIT feature on supported

			CPUs.



	ro		[KNL] Mount root device read-only on boot

	ro		[KNL] Mount root device read-only on boot





	rodata=		[KNL]

	rodata=		[KNL]

arch/x86/include/asm/cpufeatures.h

+2 −2
Original line number Original line Diff line number Diff line
@@ -186,7 +186,7 @@ 
 *

 *

 * Reuse free bits when adding new feature flags!

 * Reuse free bits when adding new feature flags!

 */

 */



#define X86_FEATURE_RING3MWAIT	( 7*32+ 0) /* Ring 3 MONITOR/MWAIT */

#define X86_FEATURE_CPB		( 7*32+ 2) /* AMD Core Performance Boost */

#define X86_FEATURE_CPB		( 7*32+ 2) /* AMD Core Performance Boost */

#define X86_FEATURE_EPB		( 7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */

#define X86_FEATURE_EPB		( 7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */

#define X86_FEATURE_CAT_L3	( 7*32+ 4) /* Cache Allocation Technology L3 */

#define X86_FEATURE_CAT_L3	( 7*32+ 4) /* Cache Allocation Technology L3 */
@@ -288,6 +288,7 @@ 
#define X86_FEATURE_AVX512VBMI  (16*32+ 1) /* AVX512 Vector Bit Manipulation instructions*/

#define X86_FEATURE_AVX512VBMI  (16*32+ 1) /* AVX512 Vector Bit Manipulation instructions*/

#define X86_FEATURE_PKU		(16*32+ 3) /* Protection Keys for Userspace */

#define X86_FEATURE_PKU		(16*32+ 3) /* Protection Keys for Userspace */

#define X86_FEATURE_OSPKE	(16*32+ 4) /* OS Protection Keys Enable */

#define X86_FEATURE_OSPKE	(16*32+ 4) /* OS Protection Keys Enable */

#define X86_FEATURE_AVX512_VPOPCNTDQ (16*32+14) /* POPCNT for vectors of DW/QW */

#define X86_FEATURE_RDPID	(16*32+ 22) /* RDPID instruction */

#define X86_FEATURE_RDPID	(16*32+ 22) /* RDPID instruction */





/* AMD-defined CPU features, CPUID level 0x80000007 (ebx), word 17 */

/* AMD-defined CPU features, CPUID level 0x80000007 (ebx), word 17 */
@@ -320,5 +321,4 @@ 
#define X86_BUG_SWAPGS_FENCE	X86_BUG(11) /* SWAPGS without input dep on GS */

#define X86_BUG_SWAPGS_FENCE	X86_BUG(11) /* SWAPGS without input dep on GS */

#define X86_BUG_MONITOR		X86_BUG(12) /* IPI required to wake up remote CPU */

#define X86_BUG_MONITOR		X86_BUG(12) /* IPI required to wake up remote CPU */

#define X86_BUG_AMD_E400	X86_BUG(13) /* CPU is among the affected by Erratum 400 */

#define X86_BUG_AMD_E400	X86_BUG(13) /* CPU is among the affected by Erratum 400 */



#endif /* _ASM_X86_CPUFEATURES_H */
 
#endif /* _ASM_X86_CPUFEATURES_H */

arch/x86/include/asm/elf.h

+9 −0
Original line number Original line Diff line number Diff line
@@ -258,6 +258,15 @@ extern int force_personality32; 




#define ELF_HWCAP		(boot_cpu_data.x86_capability[CPUID_1_EDX])

#define ELF_HWCAP		(boot_cpu_data.x86_capability[CPUID_1_EDX])





extern u32 elf_hwcap2;



/*

 * HWCAP2 supplies mask with kernel enabled CPU features, so that

 * the application can discover that it can safely use them.

 * The bits are defined in uapi/asm/hwcap2.h.

 */

#define ELF_HWCAP2		(elf_hwcap2)



/* This yields a string that ld.so will use to load implementation

/* This yields a string that ld.so will use to load implementation

   specific libraries for optimization.  This is more specific in

   specific libraries for optimization.  This is more specific in

   intent than poking at uname or /proc/cpuinfo.

   intent than poking at uname or /proc/cpuinfo.

arch/x86/include/asm/msr-index.h

+5 −0
Original line number Original line Diff line number Diff line
@@ -543,6 +543,11 @@ 
#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT	39

#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT	39

#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE		(1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT)

#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE		(1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT)





/* MISC_FEATURE_ENABLES non-architectural features */

#define MSR_MISC_FEATURE_ENABLES	0x00000140



#define MSR_MISC_FEATURE_ENABLES_RING3MWAIT_BIT		1



#define MSR_IA32_TSC_DEADLINE		0x000006E0

#define MSR_IA32_TSC_DEADLINE		0x000006E0





/* P4/Xeon+ specific */

/* P4/Xeon+ specific */

arch/x86/include/uapi/asm/hwcap2.h

0 → 100644
+7 −0
Original line number Original line Diff line number Diff line 
#ifndef _ASM_X86_HWCAP2_H

#define _ASM_X86_HWCAP2_H



/* MONITOR/MWAIT enabled in Ring 3 */

#define HWCAP2_RING3MWAIT		(1 << 0)



#endif