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Commit 8a8b86fb authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "msm: kgsl: Do not send NMI to GMU on CM3 fault"

parents 65c74ef4 20a71ac9
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+28 −26
Original line number Diff line number Diff line
@@ -2057,12 +2057,16 @@ static int _adreno_start(struct adreno_device *adreno_dev)

	/* Send OOB request to turn on the GX */
	status = gmu_core_dev_oob_set(device, oob_gpu);
	if (status)
		goto error_boot_oob_clear;
	if (status) {
		gmu_core_snapshot(device);
		goto error_oob_clear;
	}

	status = gmu_core_dev_hfi_start_msg(device);
	if (status)
	if (status) {
		gmu_core_snapshot(device);
		goto error_oob_clear;
	}

	if (device->pwrctrl.bus_control) {
		/* VBIF waiting for RAM */
@@ -2274,29 +2278,15 @@ static int adreno_stop(struct kgsl_device *device)
	error = gmu_core_dev_oob_set(device, oob_gpu);
	if (error) {
		gmu_core_dev_oob_clear(device, oob_gpu);

		if (gmu_core_regulator_isenabled(device)) {
			/* GPU is on. Try recovery */
			set_bit(GMU_FAULT, &device->gmu_core.flags);
			gmu_core_snapshot(device);
			error = -EINVAL;
		}
			goto no_gx_power;
	}

	adreno_dispatcher_stop(adreno_dev);

	adreno_ringbuffer_stop(adreno_dev);

	kgsl_pwrscale_update_stats(device);

	adreno_irqctrl(adreno_dev, 0);

	if (!IS_ERR_OR_NULL(adreno_dev->gpu_llc_slice))
		llcc_slice_deactivate(adreno_dev->gpu_llc_slice);

	if (!IS_ERR_OR_NULL(adreno_dev->gpuhtw_llc_slice))
		llcc_slice_deactivate(adreno_dev->gpuhtw_llc_slice);

	/* Save active coresight registers if applicable */
	adreno_coresight_stop(adreno_dev);

@@ -2314,19 +2304,23 @@ static int adreno_stop(struct kgsl_device *device)
	 */

	if (!error && gmu_core_dev_wait_for_lowest_idle(device)) {
		set_bit(GMU_FAULT, &device->gmu_core.flags);
		gmu_core_snapshot(device);
		/*
		 * Assume GMU hang after 10ms without responding.
		 * It shall be relative safe to clear vbif and stop
		 * MMU later. Early return in adreno_stop function
		 * will result in kernel panic in adreno_start
		 */
		error = -EINVAL;
	}

	adreno_clear_pending_transactions(device);

no_gx_power:
	adreno_dispatcher_stop(adreno_dev);

	adreno_ringbuffer_stop(adreno_dev);

	if (!IS_ERR_OR_NULL(adreno_dev->gpu_llc_slice))
		llcc_slice_deactivate(adreno_dev->gpu_llc_slice);

	if (!IS_ERR_OR_NULL(adreno_dev->gpuhtw_llc_slice))
		llcc_slice_deactivate(adreno_dev->gpuhtw_llc_slice);

	/*
	 * The halt is not cleared in the above function if we have GBIF.
	 * Clear it here if GMU is enabled as GMU stop needs access to
@@ -2996,7 +2990,15 @@ void adreno_spin_idle_debug(struct adreno_device *adreno_dev,

	dev_err(device->dev, " hwfault=%8.8X\n", hwfault);

	kgsl_device_snapshot(device, NULL, adreno_gmu_gpu_fault(adreno_dev));
	/*
	 * If CP is stuck, gmu may not perform as expected. So force a gmu
	 * snapshot which captures entire state as well as sets the gmu fault
	 * because things need to be reset anyway.
	 */
	if (gmu_core_isenabled(device))
		gmu_core_snapshot(device);
	else
		kgsl_device_snapshot(device, NULL, false);
}

/**
+2 −1
Original line number Diff line number Diff line
@@ -1609,8 +1609,9 @@ static inline int adreno_perfcntr_active_oob_get(struct kgsl_device *device)
	if (!ret) {
		ret = gmu_core_dev_oob_set(device, oob_perfcntr);
		if (ret) {
			gmu_core_snapshot(device);
			adreno_set_gpu_fault(ADRENO_DEVICE(device),
				ADRENO_GMU_FAULT);
				ADRENO_GMU_FAULT_SKIP_SNAPSHOT);
			adreno_dispatcher_schedule(device);
			kgsl_active_count_put(device);
		}
+8 −22
Original line number Diff line number Diff line
@@ -1076,8 +1076,7 @@ static int64_t a6xx_read_throttling_counters(struct adreno_device *adreno_dev)
static int a6xx_reset(struct kgsl_device *device, int fault)
{
	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
	int ret = -EINVAL;
	int i = 0;
	int ret;

	/* Use the regular reset sequence for No GMU */
	if (!gmu_core_isenabled(device))
@@ -1089,33 +1088,20 @@ static int a6xx_reset(struct kgsl_device *device, int fault)
	/* since device is officially off now clear start bit */
	clear_bit(ADRENO_DEVICE_STARTED, &adreno_dev->priv);

	/* Keep trying to start the device until it works */
	for (i = 0; i < NUM_TIMES_RESET_RETRY; i++) {
	ret = adreno_start(device, 0);
		if (!ret)
			break;

		msleep(20);
	}

	if (ret)
		return ret;

	if (i != 0)
		dev_warn(device->dev,
			      "Device hard reset tried %d tries\n", i);
	kgsl_pwrctrl_change_state(device, KGSL_STATE_ACTIVE);

	/*
	 * If active_cnt is non-zero then the system was active before
	 * going into a reset - put it back in that state
	 * If active_cnt is zero, there is no need to keep the GPU active. So,
	 * we should transition to SLUMBER.
	 */
	if (!atomic_read(&device->active_cnt))
		kgsl_pwrctrl_change_state(device, KGSL_STATE_SLUMBER);

	if (atomic_read(&device->active_cnt))
		kgsl_pwrctrl_change_state(device, KGSL_STATE_ACTIVE);
	else
		kgsl_pwrctrl_change_state(device, KGSL_STATE_NAP);

	return ret;
	return 0;
}

static void a6xx_cp_hw_err_callback(struct adreno_device *adreno_dev, int bit)
+3 −0
Original line number Diff line number Diff line
@@ -1104,6 +1104,9 @@ static int a6xx_gmu_fw_start(struct kgsl_device *device,
	/* Populate the GMU version info before GMU boots */
	load_gmu_version_info(device);

	/* Clear any previously set cm3 fault */
	atomic_set(&gmu->cm3_fault, 0);

	ret = a6xx_gmu_start(device);
	if (ret)
		return ret;
+4 −3
Original line number Diff line number Diff line
@@ -373,10 +373,11 @@ void a6xx_preemption_trigger(struct adreno_device *adreno_dev)

	return;
err:

	/* If fenced write fails, set the fault and trigger recovery */
	/* If fenced write fails, take inline snapshot and trigger recovery */
	if (!in_interrupt())
		gmu_core_snapshot(device);
	adreno_set_preempt_state(adreno_dev, ADRENO_PREEMPT_NONE);
	adreno_set_gpu_fault(adreno_dev, ADRENO_GMU_FAULT);
	adreno_set_gpu_fault(adreno_dev, ADRENO_GMU_FAULT_SKIP_SNAPSHOT);
	adreno_dispatcher_schedule(device);
	/* Clear the keep alive */
	if (gmu_core_isenabled(device))
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