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Commit 8a8b540a authored by Mika Kuoppala's avatar Mika Kuoppala Committed by Chris Wilson
Browse files

drm/i915/icl: Add command cache invalidate 



On the set of invalidations, we need to add command
cache invalidate as a new domain.

Signed-off-by: default avatarMika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190815083055.14132-2-mika.kuoppala@linux.intel.com
parent cfba6bd8

drivers/gpu/drm/i915/gt/intel_gpu_commands.h

+1 −0
Original line number Diff line number Diff line
@@ -208,6 +208,7 @@ 
#define   DISPLAY_PLANE_A           (0<<20)

#define   DISPLAY_PLANE_B           (1<<20)

#define GFX_OP_PIPE_CONTROL(len)	((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2))

#define   PIPE_CONTROL_COMMAND_CACHE_INVALIDATE		(1<<29) /* gen11+ */

#define   PIPE_CONTROL_TILE_CACHE_FLUSH			(1<<28) /* gen11+ */

#define   PIPE_CONTROL_FLUSH_L3				(1<<27)

#define   PIPE_CONTROL_GLOBAL_GTT_IVB			(1<<24) /* gen7+ */

drivers/gpu/drm/i915/gt/intel_lrc.c

+1 −0
Original line number Diff line number Diff line
@@ -2691,6 +2691,7 @@ static int gen11_emit_flush_render(struct i915_request *request, 


		flags |= PIPE_CONTROL_CS_STALL;



		flags |= PIPE_CONTROL_COMMAND_CACHE_INVALIDATE;

		flags |= PIPE_CONTROL_TLB_INVALIDATE;

		flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;

		flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;