Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 8a68d464 authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915: Store the BIT(engine->id) as the engine's mask 



In the next patch, we are introducing a broad virtual engine to encompass
multiple physical engines, losing the 1:1 nature of BIT(engine->id). To
reflect the broader set of engines implied by the virtual instance, lets
store the full bitmask.

v2: Use intel_engine_mask_t (s/ring_mask/engine_mask/)
v3: Tvrtko voted for moah churn so teach everyone to not mention ring
and use $class$instance throughout.
v4: Comment upon the disparity in bspec for using VCS1,VCS2 in gen8 and
VCS[0-4] in later gen. We opt to keep the code consistent and use
0-index naming throughout.

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190305180332.30900-1-chris@chris-wilson.co.uk
parent c8b50242

drivers/gpu/drm/i915/gvt/cmd_parser.c

+20 −24
Original line number Diff line number Diff line
@@ -391,12 +391,12 @@ struct cmd_info { 
#define F_POST_HANDLE	(1<<2)

	u32 flag;



#define R_RCS	(1 << RCS)

#define R_VCS1  (1 << VCS)

#define R_VCS2  (1 << VCS2)

#define R_RCS	BIT(RCS0)

#define R_VCS1  BIT(VCS0)

#define R_VCS2  BIT(VCS1)

#define R_VCS	(R_VCS1 | R_VCS2)

#define R_BCS	(1 << BCS)

#define R_VECS	(1 << VECS)

#define R_BCS	BIT(BCS0)

#define R_VECS	BIT(VECS0)

#define R_ALL (R_RCS | R_VCS | R_BCS | R_VECS)

	/* rings that support this cmd: BLT/RCS/VCS/VECS */

	u16 rings;
@@ -558,7 +558,7 @@ static const struct decode_info decode_info_vebox = { 
};



static const struct decode_info *ring_decode_info[I915_NUM_ENGINES][8] = {

	[RCS] = {

	[RCS0] = {

		&decode_info_mi,

		NULL,

		NULL,
@@ -569,7 +569,7 @@ static const struct decode_info *ring_decode_info[I915_NUM_ENGINES][8] = { 
		NULL,

	},



	[VCS] = {

	[VCS0] = {

		&decode_info_mi,

		NULL,

		NULL,
@@ -580,7 +580,7 @@ static const struct decode_info *ring_decode_info[I915_NUM_ENGINES][8] = { 
		NULL,

	},



	[BCS] = {

	[BCS0] = {

		&decode_info_mi,

		NULL,

		&decode_info_2d,
@@ -591,7 +591,7 @@ static const struct decode_info *ring_decode_info[I915_NUM_ENGINES][8] = { 
		NULL,

	},



	[VECS] = {

	[VECS0] = {

		&decode_info_mi,

		NULL,

		NULL,
@@ -602,7 +602,7 @@ static const struct decode_info *ring_decode_info[I915_NUM_ENGINES][8] = { 
		NULL,

	},



	[VCS2] = {

	[VCS1] = {

		&decode_info_mi,

		NULL,

		NULL,
@@ -631,8 +631,7 @@ static inline const struct cmd_info *find_cmd_entry(struct intel_gvt *gvt, 
	struct cmd_entry *e;



	hash_for_each_possible(gvt->cmd_table, e, hlist, opcode) {

		if ((opcode == e->info->opcode) &&

				(e->info->rings & (1 << ring_id)))

		if (opcode == e->info->opcode && e->info->rings & BIT(ring_id))

			return e->info;

	}

	return NULL;
@@ -943,15 +942,12 @@ static int cmd_handler_lri(struct parser_exec_state *s) 
	struct intel_gvt *gvt = s->vgpu->gvt;



	for (i = 1; i < cmd_len; i += 2) {

		if (IS_BROADWELL(gvt->dev_priv) &&

				(s->ring_id != RCS)) {

			if (s->ring_id == BCS &&

					cmd_reg(s, i) ==

					i915_mmio_reg_offset(DERRMR))

		if (IS_BROADWELL(gvt->dev_priv) && s->ring_id != RCS0) {

			if (s->ring_id == BCS0 &&

			    cmd_reg(s, i) == i915_mmio_reg_offset(DERRMR))

				ret |= 0;

			else

				ret |= (cmd_reg_inhibit(s, i)) ?

					-EBADRQC : 0;

				ret |= cmd_reg_inhibit(s, i) ? -EBADRQC : 0;

		}

		if (ret)

			break;
@@ -1047,27 +1043,27 @@ struct cmd_interrupt_event { 
};



static struct cmd_interrupt_event cmd_interrupt_events[] = {

	[RCS] = {

	[RCS0] = {

		.pipe_control_notify = RCS_PIPE_CONTROL,

		.mi_flush_dw = INTEL_GVT_EVENT_RESERVED,

		.mi_user_interrupt = RCS_MI_USER_INTERRUPT,

	},

	[BCS] = {

	[BCS0] = {

		.pipe_control_notify = INTEL_GVT_EVENT_RESERVED,

		.mi_flush_dw = BCS_MI_FLUSH_DW,

		.mi_user_interrupt = BCS_MI_USER_INTERRUPT,

	},

	[VCS] = {

	[VCS0] = {

		.pipe_control_notify = INTEL_GVT_EVENT_RESERVED,

		.mi_flush_dw = VCS_MI_FLUSH_DW,

		.mi_user_interrupt = VCS_MI_USER_INTERRUPT,

	},

	[VCS2] = {

	[VCS1] = {

		.pipe_control_notify = INTEL_GVT_EVENT_RESERVED,

		.mi_flush_dw = VCS2_MI_FLUSH_DW,

		.mi_user_interrupt = VCS2_MI_USER_INTERRUPT,

	},

	[VECS] = {

	[VECS0] = {

		.pipe_control_notify = INTEL_GVT_EVENT_RESERVED,

		.mi_flush_dw = VECS_MI_FLUSH_DW,

		.mi_user_interrupt = VECS_MI_USER_INTERRUPT,

drivers/gpu/drm/i915/gvt/execlist.c

+8 −9
Original line number Diff line number Diff line
@@ -47,17 +47,16 @@ 
		((a)->lrca == (b)->lrca))



static int context_switch_events[] = {

	[RCS] = RCS_AS_CONTEXT_SWITCH,

	[BCS] = BCS_AS_CONTEXT_SWITCH,

	[VCS] = VCS_AS_CONTEXT_SWITCH,

	[VCS2] = VCS2_AS_CONTEXT_SWITCH,

	[VECS] = VECS_AS_CONTEXT_SWITCH,

	[RCS0]  = RCS_AS_CONTEXT_SWITCH,

	[BCS0]  = BCS_AS_CONTEXT_SWITCH,

	[VCS0]  = VCS_AS_CONTEXT_SWITCH,

	[VCS1]  = VCS2_AS_CONTEXT_SWITCH,

	[VECS0] = VECS_AS_CONTEXT_SWITCH,

};



static int ring_id_to_context_switch_event(int ring_id)

static int ring_id_to_context_switch_event(unsigned int ring_id)

{

	if (WARN_ON(ring_id < RCS ||

		    ring_id >= ARRAY_SIZE(context_switch_events)))

	if (WARN_ON(ring_id >= ARRAY_SIZE(context_switch_events)))

		return -EINVAL;



	return context_switch_events[ring_id];
@@ -411,7 +410,7 @@ static int complete_execlist_workload(struct intel_vgpu_workload *workload) 
	gvt_dbg_el("complete workload %p status %d\n", workload,

			workload->status);



	if (workload->status || (vgpu->resetting_eng & ENGINE_MASK(ring_id)))

	if (workload->status || (vgpu->resetting_eng & BIT(ring_id)))

		goto out;



	if (!list_empty(workload_q_head(vgpu, ring_id))) {

drivers/gpu/drm/i915/gvt/handlers.c

+13 −13
Original line number Diff line number Diff line
@@ -323,25 +323,25 @@ static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 
	} else {

		if (data & GEN6_GRDOM_RENDER) {

			gvt_dbg_mmio("vgpu%d: request RCS reset\n", vgpu->id);

			engine_mask |= (1 << RCS);

			engine_mask |= BIT(RCS0);

		}

		if (data & GEN6_GRDOM_MEDIA) {

			gvt_dbg_mmio("vgpu%d: request VCS reset\n", vgpu->id);

			engine_mask |= (1 << VCS);

			engine_mask |= BIT(VCS0);

		}

		if (data & GEN6_GRDOM_BLT) {

			gvt_dbg_mmio("vgpu%d: request BCS Reset\n", vgpu->id);

			engine_mask |= (1 << BCS);

			engine_mask |= BIT(BCS0);

		}

		if (data & GEN6_GRDOM_VECS) {

			gvt_dbg_mmio("vgpu%d: request VECS Reset\n", vgpu->id);

			engine_mask |= (1 << VECS);

			engine_mask |= BIT(VECS0);

		}

		if (data & GEN8_GRDOM_MEDIA2) {

			gvt_dbg_mmio("vgpu%d: request VCS2 Reset\n", vgpu->id);

			if (HAS_BSD2(vgpu->gvt->dev_priv))

				engine_mask |= (1 << VCS2);

			engine_mask |= BIT(VCS1);

		}

		engine_mask &= INTEL_INFO(vgpu->gvt->dev_priv)->engine_mask;

	}



	/* vgpu_lock already hold by emulate mmio r/w */
@@ -1704,7 +1704,7 @@ static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 
			return 0;



		ret = intel_vgpu_select_submission_ops(vgpu,

			       ENGINE_MASK(ring_id),

			       BIT(ring_id),

			       INTEL_VGPU_EXECLIST_SUBMISSION);

		if (ret)

			return ret;
@@ -1724,19 +1724,19 @@ static int gvt_reg_tlb_control_handler(struct intel_vgpu *vgpu, 


	switch (offset) {

	case 0x4260:

		id = RCS;

		id = RCS0;

		break;

	case 0x4264:

		id = VCS;

		id = VCS0;

		break;

	case 0x4268:

		id = VCS2;

		id = VCS1;

		break;

	case 0x426c:

		id = BCS;

		id = BCS0;

		break;

	case 0x4270:

		id = VECS;

		id = VECS0;

		break;

	default:

		return -EINVAL;
@@ -1793,7 +1793,7 @@ static int ring_reset_ctl_write(struct intel_vgpu *vgpu, 
	MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \

	MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \

	MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \

	if (HAS_BSD2(dev_priv)) \

	if (HAS_ENGINE(dev_priv, VCS1)) \

		MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \

} while (0)

drivers/gpu/drm/i915/gvt/interrupt.c

+1 −1
Original line number Diff line number Diff line
@@ -536,7 +536,7 @@ static void gen8_init_irq( 
	SET_BIT_INFO(irq, 4, VCS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT1);

	SET_BIT_INFO(irq, 8, VCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT1);



	if (HAS_BSD2(gvt->dev_priv)) {

	if (HAS_ENGINE(gvt->dev_priv, VCS1)) {

		SET_BIT_INFO(irq, 16, VCS2_MI_USER_INTERRUPT,

			INTEL_GVT_IRQ_INFO_GT1);

		SET_BIT_INFO(irq, 20, VCS2_MI_FLUSH_DW,

drivers/gpu/drm/i915/gvt/mmio_context.c

+115 −113
Original line number Diff line number Diff line
@@ -41,102 +41,102 @@ 


/* Raw offset is appened to each line for convenience. */

static struct engine_mmio gen8_engine_mmio_list[] __cacheline_aligned = {

	{RCS, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */

	{RCS, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */

	{RCS, HWSTAM, 0x0, false}, /* 0x2098 */

	{RCS, INSTPM, 0xffff, true}, /* 0x20c0 */

	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */

	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */

	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */

	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */

	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */

	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */

	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */

	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */

	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */

	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */

	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */

	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */

	{RCS, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */

	{RCS, GEN7_GT_MODE, 0xffff, true}, /* 0x7008 */

	{RCS, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */

	{RCS, GEN7_COMMON_SLICE_CHICKEN1, 0xffff, true}, /* 0x7010 */

	{RCS, HDC_CHICKEN0, 0xffff, true}, /* 0x7300 */

	{RCS, VF_GUARDBAND, 0xffff, true}, /* 0x83a4 */



	{BCS, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */

	{BCS, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */

	{BCS, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */

	{BCS, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */

	{BCS, RING_EXCC(BLT_RING_BASE), 0x0, false}, /* 0x22028 */

	{RCS, INVALID_MMIO_REG, 0, false } /* Terminated */

	{RCS0, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */

	{RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */

	{RCS0, HWSTAM, 0x0, false}, /* 0x2098 */

	{RCS0, INSTPM, 0xffff, true}, /* 0x20c0 */

	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */

	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */

	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */

	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */

	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */

	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */

	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */

	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */

	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */

	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */

	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */

	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */

	{RCS0, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */

	{RCS0, GEN7_GT_MODE, 0xffff, true}, /* 0x7008 */

	{RCS0, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */

	{RCS0, GEN7_COMMON_SLICE_CHICKEN1, 0xffff, true}, /* 0x7010 */

	{RCS0, HDC_CHICKEN0, 0xffff, true}, /* 0x7300 */

	{RCS0, VF_GUARDBAND, 0xffff, true}, /* 0x83a4 */



	{BCS0, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */

	{BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */

	{BCS0, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */

	{BCS0, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */

	{BCS0, RING_EXCC(BLT_RING_BASE), 0x0, false}, /* 0x22028 */

	{RCS0, INVALID_MMIO_REG, 0, false } /* Terminated */

};



static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = {

	{RCS, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */

	{RCS, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */

	{RCS, HWSTAM, 0x0, false}, /* 0x2098 */

	{RCS, INSTPM, 0xffff, true}, /* 0x20c0 */

	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */

	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */

	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */

	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */

	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */

	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */

	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */

	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */

	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */

	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */

	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */

	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */

	{RCS, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */

	{RCS, GEN7_GT_MODE, 0xffff, true}, /* 0x7008 */

	{RCS, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */

	{RCS, GEN7_COMMON_SLICE_CHICKEN1, 0xffff, true}, /* 0x7010 */

	{RCS, HDC_CHICKEN0, 0xffff, true}, /* 0x7300 */

	{RCS, VF_GUARDBAND, 0xffff, true}, /* 0x83a4 */



	{RCS, GEN8_PRIVATE_PAT_LO, 0, false}, /* 0x40e0 */

	{RCS, GEN8_PRIVATE_PAT_HI, 0, false}, /* 0x40e4 */

	{RCS, GEN8_CS_CHICKEN1, 0xffff, true}, /* 0x2580 */

	{RCS, COMMON_SLICE_CHICKEN2, 0xffff, true}, /* 0x7014 */

	{RCS, GEN9_CS_DEBUG_MODE1, 0xffff, false}, /* 0x20ec */

	{RCS, GEN8_L3SQCREG4, 0, false}, /* 0xb118 */

	{RCS, GEN7_HALF_SLICE_CHICKEN1, 0xffff, true}, /* 0xe100 */

	{RCS, HALF_SLICE_CHICKEN2, 0xffff, true}, /* 0xe180 */

	{RCS, HALF_SLICE_CHICKEN3, 0xffff, true}, /* 0xe184 */

	{RCS, GEN9_HALF_SLICE_CHICKEN5, 0xffff, true}, /* 0xe188 */

	{RCS, GEN9_HALF_SLICE_CHICKEN7, 0xffff, true}, /* 0xe194 */

	{RCS, GEN8_ROW_CHICKEN, 0xffff, true}, /* 0xe4f0 */

	{RCS, TRVATTL3PTRDW(0), 0, false}, /* 0x4de0 */

	{RCS, TRVATTL3PTRDW(1), 0, false}, /* 0x4de4 */

	{RCS, TRNULLDETCT, 0, false}, /* 0x4de8 */

	{RCS, TRINVTILEDETCT, 0, false}, /* 0x4dec */

	{RCS, TRVADR, 0, false}, /* 0x4df0 */

	{RCS, TRTTE, 0, false}, /* 0x4df4 */



	{BCS, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */

	{BCS, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */

	{BCS, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */

	{BCS, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */

	{BCS, RING_EXCC(BLT_RING_BASE), 0x0, false}, /* 0x22028 */



	{VCS2, RING_EXCC(GEN8_BSD2_RING_BASE), 0xffff, false}, /* 0x1c028 */



	{VECS, RING_EXCC(VEBOX_RING_BASE), 0xffff, false}, /* 0x1a028 */



	{RCS, GEN8_HDC_CHICKEN1, 0xffff, true}, /* 0x7304 */

	{RCS, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */

	{RCS, GEN7_UCGCTL4, 0x0, false}, /* 0x940c */

	{RCS, GAMT_CHKN_BIT_REG, 0x0, false}, /* 0x4ab8 */



	{RCS, GEN9_GAMT_ECO_REG_RW_IA, 0x0, false}, /* 0x4ab0 */

	{RCS, GEN9_CSFE_CHICKEN1_RCS, 0xffff, false}, /* 0x20d4 */



	{RCS, GEN8_GARBCNTL, 0x0, false}, /* 0xb004 */

	{RCS, GEN7_FF_THREAD_MODE, 0x0, false}, /* 0x20a0 */

	{RCS, FF_SLICE_CS_CHICKEN2, 0xffff, false}, /* 0x20e4 */

	{RCS, INVALID_MMIO_REG, 0, false } /* Terminated */

	{RCS0, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */

	{RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */

	{RCS0, HWSTAM, 0x0, false}, /* 0x2098 */

	{RCS0, INSTPM, 0xffff, true}, /* 0x20c0 */

	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */

	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */

	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */

	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */

	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */

	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */

	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */

	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */

	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */

	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */

	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */

	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */

	{RCS0, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */

	{RCS0, GEN7_GT_MODE, 0xffff, true}, /* 0x7008 */

	{RCS0, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */

	{RCS0, GEN7_COMMON_SLICE_CHICKEN1, 0xffff, true}, /* 0x7010 */

	{RCS0, HDC_CHICKEN0, 0xffff, true}, /* 0x7300 */

	{RCS0, VF_GUARDBAND, 0xffff, true}, /* 0x83a4 */



	{RCS0, GEN8_PRIVATE_PAT_LO, 0, false}, /* 0x40e0 */

	{RCS0, GEN8_PRIVATE_PAT_HI, 0, false}, /* 0x40e4 */

	{RCS0, GEN8_CS_CHICKEN1, 0xffff, true}, /* 0x2580 */

	{RCS0, COMMON_SLICE_CHICKEN2, 0xffff, true}, /* 0x7014 */

	{RCS0, GEN9_CS_DEBUG_MODE1, 0xffff, false}, /* 0x20ec */

	{RCS0, GEN8_L3SQCREG4, 0, false}, /* 0xb118 */

	{RCS0, GEN7_HALF_SLICE_CHICKEN1, 0xffff, true}, /* 0xe100 */

	{RCS0, HALF_SLICE_CHICKEN2, 0xffff, true}, /* 0xe180 */

	{RCS0, HALF_SLICE_CHICKEN3, 0xffff, true}, /* 0xe184 */

	{RCS0, GEN9_HALF_SLICE_CHICKEN5, 0xffff, true}, /* 0xe188 */

	{RCS0, GEN9_HALF_SLICE_CHICKEN7, 0xffff, true}, /* 0xe194 */

	{RCS0, GEN8_ROW_CHICKEN, 0xffff, true}, /* 0xe4f0 */

	{RCS0, TRVATTL3PTRDW(0), 0, false}, /* 0x4de0 */

	{RCS0, TRVATTL3PTRDW(1), 0, false}, /* 0x4de4 */

	{RCS0, TRNULLDETCT, 0, false}, /* 0x4de8 */

	{RCS0, TRINVTILEDETCT, 0, false}, /* 0x4dec */

	{RCS0, TRVADR, 0, false}, /* 0x4df0 */

	{RCS0, TRTTE, 0, false}, /* 0x4df4 */



	{BCS0, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */

	{BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */

	{BCS0, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */

	{BCS0, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */

	{BCS0, RING_EXCC(BLT_RING_BASE), 0x0, false}, /* 0x22028 */



	{VCS1, RING_EXCC(GEN8_BSD2_RING_BASE), 0xffff, false}, /* 0x1c028 */



	{VECS0, RING_EXCC(VEBOX_RING_BASE), 0xffff, false}, /* 0x1a028 */



	{RCS0, GEN8_HDC_CHICKEN1, 0xffff, true}, /* 0x7304 */

	{RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */

	{RCS0, GEN7_UCGCTL4, 0x0, false}, /* 0x940c */

	{RCS0, GAMT_CHKN_BIT_REG, 0x0, false}, /* 0x4ab8 */



	{RCS0, GEN9_GAMT_ECO_REG_RW_IA, 0x0, false}, /* 0x4ab0 */

	{RCS0, GEN9_CSFE_CHICKEN1_RCS, 0xffff, false}, /* 0x20d4 */



	{RCS0, GEN8_GARBCNTL, 0x0, false}, /* 0xb004 */

	{RCS0, GEN7_FF_THREAD_MODE, 0x0, false}, /* 0x20a0 */

	{RCS0, FF_SLICE_CS_CHICKEN2, 0xffff, false}, /* 0x20e4 */

	{RCS0, INVALID_MMIO_REG, 0, false } /* Terminated */

};



static struct {
@@ -149,11 +149,11 @@ static void load_render_mocs(struct drm_i915_private *dev_priv) 
{

	i915_reg_t offset;

	u32 regs[] = {

		[RCS] = 0xc800,

		[VCS] = 0xc900,

		[VCS2] = 0xca00,

		[BCS] = 0xcc00,

		[VECS] = 0xcb00,

		[RCS0]  = 0xc800,

		[VCS0]  = 0xc900,

		[VCS1]  = 0xca00,

		[BCS0]  = 0xcc00,

		[VECS0] = 0xcb00,

	};

	int ring_id, i;
@@ -301,7 +301,7 @@ int intel_vgpu_restore_inhibit_context(struct intel_vgpu *vgpu, 
		goto out;



	/* no MOCS register in context except render engine */

	if (req->engine->id != RCS)

	if (req->engine->id != RCS0)

		goto out;



	ret = restore_render_mocs_control_for_inhibit(vgpu, req);
@@ -331,11 +331,11 @@ static void handle_tlb_pending_event(struct intel_vgpu *vgpu, int ring_id) 
	enum forcewake_domains fw;

	i915_reg_t reg;

	u32 regs[] = {

		[RCS] = 0x4260,

		[VCS] = 0x4264,

		[VCS2] = 0x4268,

		[BCS] = 0x426c,

		[VECS] = 0x4270,

		[RCS0]  = 0x4260,

		[VCS0]  = 0x4264,

		[VCS1]  = 0x4268,

		[BCS0]  = 0x426c,

		[VECS0] = 0x4270,

	};



	if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
@@ -353,7 +353,7 @@ static void handle_tlb_pending_event(struct intel_vgpu *vgpu, int ring_id) 
	 */

	fw = intel_uncore_forcewake_for_reg(dev_priv, reg,

					    FW_REG_READ | FW_REG_WRITE);

	if (ring_id == RCS && (INTEL_GEN(dev_priv) >= 9))

	if (ring_id == RCS0 && INTEL_GEN(dev_priv) >= 9)

		fw |= FORCEWAKE_RENDER;



	intel_uncore_forcewake_get(dev_priv, fw);
@@ -378,11 +378,11 @@ static void switch_mocs(struct intel_vgpu *pre, struct intel_vgpu *next, 
	u32 old_v, new_v;



	u32 regs[] = {

		[RCS] = 0xc800,

		[VCS] = 0xc900,

		[VCS2] = 0xca00,

		[BCS] = 0xcc00,

		[VECS] = 0xcb00,

		[RCS0]  = 0xc800,

		[VCS0]  = 0xc900,

		[VCS1]  = 0xca00,

		[BCS0]  = 0xcc00,

		[VECS0] = 0xcb00,

	};

	int i;
@@ -390,8 +390,10 @@ static void switch_mocs(struct intel_vgpu *pre, struct intel_vgpu *next, 
	if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))

		return;



	if ((IS_KABYLAKE(dev_priv)  || IS_BROXTON(dev_priv)

		|| IS_COFFEELAKE(dev_priv)) && ring_id == RCS)

	if (ring_id == RCS0 &&

	    (IS_KABYLAKE(dev_priv) ||

	     IS_BROXTON(dev_priv) ||

	     IS_COFFEELAKE(dev_priv)))

		return;



	if (!pre && !gen9_render_mocs.initialized)
@@ -414,7 +416,7 @@ static void switch_mocs(struct intel_vgpu *pre, struct intel_vgpu *next, 
		offset.reg += 4;

	}



	if (ring_id == RCS) {

	if (ring_id == RCS0) {

		l3_offset.reg = 0xb020;

		for (i = 0; i < GEN9_MOCS_SIZE / 2; i++) {

			if (pre)