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Commit 8a4e8410 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge changes I00518e84,I08f66c0e,I2948bc6e,I21bc67b4,I79acaf83,I2f8ffe6e into... 

Merge changes I00518e84,I08f66c0e,I2948bc6e,I21bc67b4,I79acaf83,I2f8ffe6e into display-kernel.lnx.1.0

* changes:
  disp: msm: sde: use device tree node to enable INTF TE capability
  disp: msm: sde: refactor sde_hw_interrupts to use offsets from catalog
  disp: msm: sde: get INTF TEAR IRQ offsets from device tree
  disp: msm: sde: rename MDSS_INTR_* enums to SDE_INTR_*
  disp: msm: sde: add Lahaina version checks
  disp: msm: sde: move all hw version checks in to the catalog
parents 8e2dde84 18b3e27f

msm/sde/sde_encoder_phys_cmd.c

+11 −4
Original line number Diff line number Diff line
@@ -1801,6 +1801,15 @@ static void sde_encoder_phys_cmd_init_ops(struct sde_encoder_phys_ops *ops) 
	ops->collect_misr = sde_encoder_helper_collect_misr;

}



static inline bool sde_encoder_phys_cmd_intf_te_supported(

		const struct sde_mdss_cfg *sde_cfg, enum sde_intf idx)

{

	if (sde_cfg && ((idx - INTF_0) < sde_cfg->intf_count))

		return test_bit(SDE_INTF_TE,

				&(sde_cfg->intf[idx - INTF_0].features));

	return false;

}



struct sde_encoder_phys *sde_encoder_phys_cmd_init(

		struct sde_enc_phys_init_params *p)

{
@@ -1841,10 +1850,8 @@ struct sde_encoder_phys *sde_encoder_phys_cmd_init( 
	sde_encoder_phys_cmd_init_ops(&phys_enc->ops);

	phys_enc->comp_type = p->comp_type;



	if (sde_hw_intf_te_supported(phys_enc->sde_kms->catalog))

		phys_enc->has_intf_te = true;

	else

		phys_enc->has_intf_te = false;

	phys_enc->has_intf_te = sde_encoder_phys_cmd_intf_te_supported(

			phys_enc->sde_kms->catalog, phys_enc->intf_idx);



	for (i = 0; i < INTR_IDX_MAX; i++) {

		irq = &phys_enc->irq[i];

msm/sde/sde_hw_catalog.c

+164 −25
Original line number Diff line number Diff line
@@ -277,6 +277,7 @@ enum { 
	INTF_LEN,

	INTF_PREFETCH,

	INTF_TYPE,

	INTF_TE_IRQ,

	INTF_PROP_MAX,

};
@@ -709,6 +710,7 @@ static struct sde_prop_type intf_prop[] = { 
	{INTF_PREFETCH, "qcom,sde-intf-max-prefetch-lines", false,

						PROP_TYPE_U32_ARRAY},

	{INTF_TYPE, "qcom,sde-intf-type", false, PROP_TYPE_STRING_ARRAY},

	{INTF_TE_IRQ, "qcom,sde-intf-tear-irq-off", false, PROP_TYPE_U32_ARRAY},

};



static struct sde_prop_type wb_prop[] = {
@@ -1058,6 +1060,74 @@ static int _read_dt_entry(struct device_node *np, 
	return rc;

}



static int _add_to_irq_offset_list(struct sde_mdss_cfg *sde_cfg,

		enum sde_intr_hwblk_type blk_type, u32 instance, u32 offset)

{

	struct sde_intr_irq_offsets *item = NULL;

	bool err = false;



	switch (blk_type) {

	case SDE_INTR_HWBLK_TOP:

		if (instance >= SDE_INTR_TOP_MAX)

			err = true;

		break;

	case SDE_INTR_HWBLK_INTF:

		if (instance >= INTF_MAX)

			err = true;

		break;

	case SDE_INTR_HWBLK_AD4:

		if (instance >= AD_MAX)

			err = true;

		break;

	case SDE_INTR_HWBLK_INTF_TEAR:

		if (instance >= INTF_MAX)

			err = true;

		break;

	case SDE_INTR_HWBLK_LTM:

		if (instance >= LTM_MAX)

			err = true;

		break;

	default:

		SDE_ERROR("invalid hwblk_type: %d", blk_type);

		return -EINVAL;

	}



	if (err) {

		SDE_ERROR("unable to map instance %d for blk type %d",

				instance, blk_type);

		return -EINVAL;

	}



	/* Check for existing list entry */

	item = sde_hw_intr_list_lookup(sde_cfg, blk_type, instance);

	if (IS_ERR_OR_NULL(item)) {

		SDE_DEBUG("adding intr type %d idx %d offset 0x%x\n",

				blk_type, instance, offset);

	} else if (item->base_offset == offset) {

		SDE_INFO("duplicate intr %d/%d offset 0x%x, skipping\n",

				blk_type, instance, offset);

		return 0;

	} else {

		SDE_ERROR("type %d, idx %d in list with offset 0x%x != 0x%x\n",

				blk_type, instance, item->base_offset, offset);

		return -EINVAL;

	}



	item = kzalloc(sizeof(*item), GFP_KERNEL);

	if (!item) {

		SDE_ERROR("memory allocation failed!\n");

		return -ENOMEM;

	}



	INIT_LIST_HEAD(&item->list);

	item->type = blk_type;

	item->instance_idx = instance;

	item->base_offset = offset;

	list_add_tail(&item->list, &sde_cfg->irq_offset_list);



	return 0;

}



static void _sde_sspp_setup_vig(struct sde_mdss_cfg *sde_cfg,

	struct sde_sspp_cfg *sspp, struct sde_sspp_sub_blks *sblk,

	bool *prop_exists, struct sde_prop_value *prop_value, u32 *vig_count)
@@ -1210,6 +1280,9 @@ static void _sde_sspp_setup_vig(struct sde_mdss_cfg *sde_cfg, 
		sblk->llcc_slice_size =

			sde_cfg->sc_cfg.llcc_slice_size;

	}



	if (sde_cfg->inline_disable_const_clr)

		set_bit(SDE_SSPP_INLINE_CONST_CLR, &sspp->features);

}



static void _sde_sspp_setup_rgb(struct sde_mdss_cfg *sde_cfg,
@@ -1850,6 +1923,8 @@ static int sde_mixer_parse_dt(struct device_node *np, 
			set_bit(SDE_MIXER_SOURCESPLIT, &mixer->features);

		if (sde_cfg->has_dim_layer)

			set_bit(SDE_DIM_LAYER, &mixer->features);

		if (sde_cfg->has_mixer_combined_alpha)

			set_bit(SDE_MIXER_COMBINED_ALPHA, &mixer->features);



		of_property_read_string_index(np,

			mixer_prop[MIXER_DISP].prop_name, i, &disp_pref);
@@ -1941,6 +2016,11 @@ static int sde_intf_parse_dt(struct device_node *np, 
		if (!prop_exists[INTF_LEN])

			intf->len = DEFAULT_SDE_HW_BLOCK_LEN;



		rc = _add_to_irq_offset_list(sde_cfg, SDE_INTR_HWBLK_INTF,

				intf->id, intf->base);

		if (rc)

			goto end;



		intf->prog_fetch_lines_worst_case =

				!prop_exists[INTF_PREFETCH] ?

				sde_cfg->perf.min_prefill_lines :
@@ -1968,12 +2048,20 @@ static int sde_intf_parse_dt(struct device_node *np, 
		if (IS_SDE_CTL_REV_100(sde_cfg->ctl_rev))

			set_bit(SDE_INTF_INPUT_CTRL, &intf->features);



		if (IS_SDE_MAJOR_SAME((sde_cfg->hwversion),

				SDE_HW_VER_500) ||

				IS_SDE_MAJOR_SAME((sde_cfg->hwversion),

				SDE_HW_VER_600))

		if (prop_exists[INTF_TE_IRQ])

			intf->te_irq_offset = PROP_VALUE_ACCESS(prop_value,

					INTF_TE_IRQ, i);



		if (intf->te_irq_offset) {

			rc = _add_to_irq_offset_list(sde_cfg,

					SDE_INTR_HWBLK_INTF_TEAR,

					intf->id, intf->te_irq_offset);

			if (rc)

				goto end;



			set_bit(SDE_INTF_TE, &intf->features);

		}

	}



end:

	kfree(prop_value);
@@ -2437,6 +2525,11 @@ static int sde_dspp_parse_dt(struct device_node *np, 
			sblk->ad.version = PROP_VALUE_ACCESS(ad_prop_value,

				AD_VERSION, 0);

			set_bit(SDE_DSPP_AD, &dspp->features);

			rc = _add_to_irq_offset_list(sde_cfg,

					SDE_INTR_HWBLK_AD4, dspp->id,

					dspp->base + sblk->ad.base);

			if (rc)

				goto end;

		}



		sblk->ltm.id = SDE_DSPP_LTM;
@@ -2448,6 +2541,11 @@ static int sde_dspp_parse_dt(struct device_node *np, 
			sblk->ltm.version = PROP_VALUE_ACCESS(ltm_prop_value,

				LTM_VERSION, 0);

			set_bit(SDE_DSPP_LTM, &dspp->features);

			rc = _add_to_irq_offset_list(sde_cfg,

					SDE_INTR_HWBLK_LTM, dspp->id,

					dspp->base + sblk->ltm.base);

			if (rc)

				goto end;

		}



	}
@@ -2902,6 +3000,8 @@ static int _sde_vbif_populate(struct sde_mdss_cfg *sde_cfg, 
	for (j = 0; j < prop_count[VBIF_MEMTYPE_1]; j++)

		vbif->memtype[k++] = PROP_VALUE_ACCESS(

				prop_value, VBIF_MEMTYPE_1, j);

	if (sde_cfg->vbif_disable_inner_outer_shareable)

		set_bit(SDE_VBIF_DISABLE_SHAREABLE, &vbif->features);



	return 0;

}
@@ -3363,6 +3463,21 @@ static int sde_top_parse_dt(struct device_node *np, struct sde_mdss_cfg *cfg) 
	if (major_version < SDE_HW_MAJOR(SDE_HW_VER_500))

		set_bit(SDE_MDP_VSYNC_SEL, &cfg->mdp[0].features);



	rc = _add_to_irq_offset_list(cfg, SDE_INTR_HWBLK_TOP,

			SDE_INTR_TOP_INTR, cfg->mdp[0].base);

	if (rc)

		goto end;



	rc = _add_to_irq_offset_list(cfg, SDE_INTR_HWBLK_TOP,

			SDE_INTR_TOP_INTR2, cfg->mdp[0].base);

	if (rc)

		goto end;



	rc = _add_to_irq_offset_list(cfg, SDE_INTR_HWBLK_TOP,

			SDE_INTR_TOP_HIST_INTR, cfg->mdp[0].base);

	if (rc)

		goto end;



	if (prop_exists[SEC_SID_MASK]) {

		cfg->sec_sid_mask_count = prop_count[SEC_SID_MASK];

		for (i = 0; i < cfg->sec_sid_mask_count; i++)
@@ -4045,29 +4160,28 @@ static void _sde_hw_setup_uidle(struct sde_uidle_cfg *uidle_cfg) 


static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev)

{

	int i, rc = 0;

	int rc = 0;



	if (!sde_cfg)

		return -EINVAL;



	for (i = 0; i < MDSS_INTR_MAX; i++)

		set_bit(i, sde_cfg->mdss_irqs);

	/* default settings for *MOST* targets */

	sde_cfg->has_mixer_combined_alpha = true;



	/* target specific settings */

	if (IS_MSM8996_TARGET(hw_rev)) {

		sde_cfg->perf.min_prefill_lines = 21;

		clear_bit(MDSS_INTR_LTM_0_INTR, sde_cfg->mdss_irqs);

		clear_bit(MDSS_INTR_LTM_1_INTR, sde_cfg->mdss_irqs);

		sde_cfg->has_decimation = true;

		sde_cfg->has_mixer_combined_alpha = false;

	} else if (IS_MSM8998_TARGET(hw_rev)) {

		sde_cfg->has_wb_ubwc = true;

		sde_cfg->perf.min_prefill_lines = 25;

		sde_cfg->vbif_qos_nlvl = 4;

		sde_cfg->ts_prefill_rev = 1;

		clear_bit(MDSS_INTR_LTM_0_INTR, sde_cfg->mdss_irqs);

		clear_bit(MDSS_INTR_LTM_1_INTR, sde_cfg->mdss_irqs);

		sde_cfg->has_decimation = true;

		sde_cfg->has_cursor = true;

		sde_cfg->has_hdr = true;

		sde_cfg->has_mixer_combined_alpha = false;

	} else if (IS_SDM845_TARGET(hw_rev)) {

		sde_cfg->has_wb_ubwc = true;

		sde_cfg->has_cwb_support = true;
@@ -4076,8 +4190,6 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev) 
		sde_cfg->ts_prefill_rev = 2;

		sde_cfg->sui_misr_supported = true;

		sde_cfg->sui_block_xin_mask = 0x3F71;

		clear_bit(MDSS_INTR_LTM_0_INTR, sde_cfg->mdss_irqs);

		clear_bit(MDSS_INTR_LTM_1_INTR, sde_cfg->mdss_irqs);

		sde_cfg->has_decimation = true;

		sde_cfg->has_hdr = true;

		sde_cfg->has_vig_p010 = true;
@@ -4086,8 +4198,6 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev) 
		sde_cfg->perf.min_prefill_lines = 24;

		sde_cfg->vbif_qos_nlvl = 8;

		sde_cfg->ts_prefill_rev = 2;

		clear_bit(MDSS_INTR_LTM_0_INTR, sde_cfg->mdss_irqs);

		clear_bit(MDSS_INTR_LTM_1_INTR, sde_cfg->mdss_irqs);

		sde_cfg->has_decimation = true;

		sde_cfg->has_hdr = true;

		sde_cfg->has_vig_p010 = true;
@@ -4110,9 +4220,8 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev) 
		sde_cfg->has_sui_blendstage = true;

		sde_cfg->has_qos_fl_nocalc = true;

		sde_cfg->has_3d_merge_reset = true;

		clear_bit(MDSS_INTR_LTM_0_INTR, sde_cfg->mdss_irqs);

		clear_bit(MDSS_INTR_LTM_1_INTR, sde_cfg->mdss_irqs);

		sde_cfg->has_decimation = true;

		sde_cfg->vbif_disable_inner_outer_shareable = true;

	} else if (IS_SDMSHRIKE_TARGET(hw_rev)) {

		sde_cfg->has_wb_ubwc = true;

		sde_cfg->perf.min_prefill_lines = 24;
@@ -4120,8 +4229,6 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev) 
		sde_cfg->ts_prefill_rev = 2;

		sde_cfg->ctl_rev = SDE_CTL_CFG_VERSION_1_0_0;

		sde_cfg->delay_prg_fetch_start = true;

		clear_bit(MDSS_INTR_LTM_0_INTR, sde_cfg->mdss_irqs);

		clear_bit(MDSS_INTR_LTM_1_INTR, sde_cfg->mdss_irqs);

		sde_cfg->has_decimation = true;

		sde_cfg->has_hdr = true;

		sde_cfg->has_vig_p010 = true;
@@ -4140,10 +4247,9 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev) 
		sde_cfg->has_sui_blendstage = true;

		sde_cfg->has_qos_fl_nocalc = true;

		sde_cfg->has_3d_merge_reset = true;

		clear_bit(MDSS_INTR_LTM_0_INTR, sde_cfg->mdss_irqs);

		clear_bit(MDSS_INTR_LTM_1_INTR, sde_cfg->mdss_irqs);

		sde_cfg->has_hdr = true;

		sde_cfg->has_vig_p010 = true;

		sde_cfg->vbif_disable_inner_outer_shareable = true;

	} else if (IS_SDMMAGPIE_TARGET(hw_rev)) {

		sde_cfg->has_cwb_support = true;

		sde_cfg->has_wb_ubwc = true;
@@ -4159,6 +4265,7 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev) 
		sde_cfg->has_sui_blendstage = true;

		sde_cfg->has_qos_fl_nocalc = true;

		sde_cfg->has_3d_merge_reset = true;

		sde_cfg->vbif_disable_inner_outer_shareable = true;

	} else if (IS_KONA_TARGET(hw_rev)) {

		sde_cfg->has_cwb_support = true;

		sde_cfg->has_wb_ubwc = true;
@@ -4174,8 +4281,6 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev) 
		sde_cfg->has_sui_blendstage = true;

		sde_cfg->has_qos_fl_nocalc = true;

		sde_cfg->has_3d_merge_reset = true;

		clear_bit(MDSS_INTR_AD4_0_INTR, sde_cfg->mdss_irqs);

		clear_bit(MDSS_INTR_AD4_1_INTR, sde_cfg->mdss_irqs);

		sde_cfg->has_hdr = true;

		sde_cfg->has_hdr_plus = true;

		set_bit(SDE_MDP_DHDR_MEMPOOL, &sde_cfg->mdp[0].features);
@@ -4191,6 +4296,7 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev) 
		sde_cfg->true_inline_prefill_lines_nv12 = 32;

		sde_cfg->true_inline_prefill_lines = 48;

		sde_cfg->uidle_cfg.uidle_rev = SDE_UIDLE_VERSION_1_0_0;

		sde_cfg->inline_disable_const_clr = true;

	} else if (IS_SAIPAN_TARGET(hw_rev)) {

		sde_cfg->has_cwb_support = true;

		sde_cfg->has_wb_ubwc = true;
@@ -4206,8 +4312,6 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev) 
		sde_cfg->has_sui_blendstage = true;

		sde_cfg->has_qos_fl_nocalc = true;

		sde_cfg->has_3d_merge_reset = true;

		clear_bit(MDSS_INTR_AD4_0_INTR, sde_cfg->mdss_irqs);

		clear_bit(MDSS_INTR_AD4_1_INTR, sde_cfg->mdss_irqs);

		sde_cfg->has_hdr = true;

		sde_cfg->has_hdr_plus = true;

		set_bit(SDE_MDP_DHDR_MEMPOOL, &sde_cfg->mdp[0].features);
@@ -4222,6 +4326,7 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev) 
		sde_cfg->true_inline_prefill_fudge_lines = 2;

		sde_cfg->true_inline_prefill_lines_nv12 = 32;

		sde_cfg->true_inline_prefill_lines = 48;

		sde_cfg->inline_disable_const_clr = true;

	} else if (IS_SDMTRINKET_TARGET(hw_rev)) {

		sde_cfg->has_cwb_support = true;

		sde_cfg->has_qsync = true;
@@ -4235,6 +4340,7 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev) 
		sde_cfg->sui_block_xin_mask = 0xC61;

		sde_cfg->has_hdr = false;

		sde_cfg->has_sui_blendstage = true;

		sde_cfg->vbif_disable_inner_outer_shareable = true;

	} else if (IS_BENGAL_TARGET(hw_rev)) {

		sde_cfg->has_cwb_support = false;

		sde_cfg->has_qsync = true;
@@ -4248,6 +4354,36 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev) 
		sde_cfg->sui_block_xin_mask = 0xC01;

		sde_cfg->has_hdr = false;

		sde_cfg->has_sui_blendstage = true;

		sde_cfg->vbif_disable_inner_outer_shareable = true;

	} else if (IS_LAHAINA_TARGET(hw_rev)) {

		sde_cfg->has_cwb_support = true;

		sde_cfg->has_wb_ubwc = true;

		sde_cfg->has_qsync = true;

		sde_cfg->perf.min_prefill_lines = 24;

		sde_cfg->vbif_qos_nlvl = 8;

		sde_cfg->ts_prefill_rev = 2;

		sde_cfg->ctl_rev = SDE_CTL_CFG_VERSION_1_0_0;

		sde_cfg->delay_prg_fetch_start = true;

		sde_cfg->sui_ns_allowed = true;

		sde_cfg->sui_misr_supported = true;

		sde_cfg->sui_block_xin_mask = 0x3F71;

		sde_cfg->has_3d_merge_reset = true;

		sde_cfg->has_hdr = true;

		sde_cfg->has_hdr_plus = true;

		set_bit(SDE_MDP_DHDR_MEMPOOL, &sde_cfg->mdp[0].features);

		sde_cfg->has_vig_p010 = true;

		sde_cfg->true_inline_rot_rev = SDE_INLINE_ROT_VERSION_1_0_0;

		sde_cfg->true_inline_dwnscale_rt_num =

			MAX_DOWNSCALE_RATIO_INLINE_ROT_RT_NUMERATOR;

		sde_cfg->true_inline_dwnscale_rt_denom =

			MAX_DOWNSCALE_RATIO_INLINE_ROT_RT_DENOMINATOR;

		sde_cfg->true_inline_dwnscale_nrt =

			MAX_DOWNSCALE_RATIO_INLINE_ROT_NRT_DEFAULT;

		sde_cfg->true_inline_prefill_fudge_lines = 2;

		sde_cfg->true_inline_prefill_lines_nv12 = 32;

		sde_cfg->true_inline_prefill_lines = 48;

		sde_cfg->uidle_cfg.uidle_rev = SDE_UIDLE_VERSION_1_0_0;

		sde_cfg->vbif_disable_inner_outer_shareable = true;

	} else {

		SDE_ERROR("unsupported chipset id:%X\n", hw_rev);

		sde_cfg->perf.min_prefill_lines = 0xffff;
@@ -4328,6 +4464,8 @@ void sde_hw_catalog_deinit(struct sde_mdss_cfg *sde_cfg) 
	if (!sde_cfg)

		return;



	sde_hw_catalog_irq_offset_list_delete(&sde_cfg->irq_offset_list);



	for (i = 0; i < sde_cfg->sspp_count; i++)

		kfree(sde_cfg->sspp[i].sblk);
@@ -4388,6 +4526,7 @@ struct sde_mdss_cfg *sde_hw_catalog_init(struct drm_device *dev, u32 hw_rev) 
		return ERR_PTR(-ENOMEM);



	sde_cfg->hwversion = hw_rev;

	INIT_LIST_HEAD(&sde_cfg->irq_offset_list);



	rc = _sde_hardware_pre_caps(sde_cfg, hw_rev);

	if (rc)

msm/sde/sde_hw_catalog.h

+73 −47
Original line number Diff line number Diff line
@@ -30,30 +30,26 @@ 
#define SDE_HW_STEP(rev)		((rev) & 0xFFFF)

#define SDE_HW_MAJOR_MINOR(rev)		((rev) >> 16)



#define SDE_HW_VER_170	SDE_HW_VER(1, 7, 0) /* 8996 */

#define SDE_HW_VER_300	SDE_HW_VER(3, 0, 0) /* 8998 */

#define SDE_HW_VER_400	SDE_HW_VER(4, 0, 0) /* sdm845 */

#define SDE_HW_VER_410	SDE_HW_VER(4, 1, 0) /* sdm670 */

#define SDE_HW_VER_500	SDE_HW_VER(5, 0, 0) /* sm8150 */

#define SDE_HW_VER_510	SDE_HW_VER(5, 1, 0) /* sdmshrike */

#define SDE_HW_VER_520	SDE_HW_VER(5, 2, 0) /* sdmmagpie */

#define SDE_HW_VER_530	SDE_HW_VER(5, 3, 0) /* sm6150 */

#define SDE_HW_VER_540	SDE_HW_VER(5, 4, 0) /* sdmtrinket */

#define SDE_HW_VER_600	SDE_HW_VER(6, 0, 0) /* kona */

#define SDE_HW_VER_610	SDE_HW_VER(6, 1, 0) /* sm7250 */

#define SDE_HW_VER_630	SDE_HW_VER(6, 3, 0) /* bengal */

#define SDE_HW_VER_700	SDE_HW_VER(7, 0, 0) /* lahaina */



/* Avoid using below IS_XXX macros outside catalog, use feature bit instead */

#define IS_SDE_MAJOR_SAME(rev1, rev2)   \

		(SDE_HW_MAJOR((rev1)) == SDE_HW_MAJOR((rev2)))



#define IS_SDE_MAJOR_MINOR_SAME(rev1, rev2)   \

		(SDE_HW_MAJOR_MINOR((rev1)) == SDE_HW_MAJOR_MINOR((rev2)))



#define SDE_HW_VER_170	SDE_HW_VER(1, 7, 0) /* 8996 v1.0 */

#define SDE_HW_VER_171	SDE_HW_VER(1, 7, 1) /* 8996 v2.0 */

#define SDE_HW_VER_172	SDE_HW_VER(1, 7, 2) /* 8996 v3.0 */

#define SDE_HW_VER_300	SDE_HW_VER(3, 0, 0) /* 8998 v1.0 */

#define SDE_HW_VER_301	SDE_HW_VER(3, 0, 1) /* 8998 v1.1 */

#define SDE_HW_VER_400	SDE_HW_VER(4, 0, 0) /* sdm845 v1.0 */

#define SDE_HW_VER_401	SDE_HW_VER(4, 0, 1) /* sdm845 v2.0 */

#define SDE_HW_VER_410	SDE_HW_VER(4, 1, 0) /* sdm670 v1.0 */

#define SDE_HW_VER_500	SDE_HW_VER(5, 0, 0) /* sm8150 v1.0 */

#define SDE_HW_VER_501	SDE_HW_VER(5, 0, 1) /* sm8150 v2.0 */

#define SDE_HW_VER_510	SDE_HW_VER(5, 1, 0) /* sdmshrike v1.0 */

#define SDE_HW_VER_520	SDE_HW_VER(5, 2, 0) /* sdmmagpie v1.0 */

#define SDE_HW_VER_530	SDE_HW_VER(5, 3, 0) /* sm6150 v1.0 */

#define SDE_HW_VER_540	SDE_HW_VER(5, 4, 0) /* sdmtrinket v1.0 */

#define SDE_HW_VER_600	SDE_HW_VER(6, 0, 0) /* kona */

#define SDE_HW_VER_610	SDE_HW_VER(6, 1, 0) /* sm7250 */

#define SDE_HW_VER_630	SDE_HW_VER(6, 3, 0) /* bengal */



#define IS_MSM8996_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_170)

#define IS_MSM8998_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_300)

#define IS_SDM845_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_400)
@@ -66,6 +62,7 @@ 
#define IS_KONA_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_600)

#define IS_SAIPAN_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_610)

#define IS_BENGAL_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_630)

#define IS_LAHAINA_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_700)



#define SDE_HW_BLK_NAME_LEN	16
@@ -138,26 +135,30 @@ enum { 
#define SSPP_SYS_CACHE_NO_ALLOC	BIT(4)



/**

 * SDE INTERRUPTS - maintains the possible hw irq's allowed by HW

 * The order in this enum must match the order of the irqs defined

 * by 'sde_irq_map'

 */

enum sde_intr_enum {

	MDSS_INTR_SSPP_TOP0_INTR,

	MDSS_INTR_SSPP_TOP0_INTR2,

	MDSS_INTF_TEAR_1_INTR,

	MDSS_INTF_TEAR_2_INTR,

	MDSS_INTR_SSPP_TOP0_HIST_INTR,

	MDSS_INTR_INTF_0_INTR,

	MDSS_INTR_INTF_1_INTR,

	MDSS_INTR_INTF_2_INTR,

	MDSS_INTR_INTF_3_INTR,

	MDSS_INTR_INTF_4_INTR,

	MDSS_INTR_AD4_0_INTR,

	MDSS_INTR_AD4_1_INTR,

	MDSS_INTR_LTM_0_INTR,

	MDSS_INTR_LTM_1_INTR,

	MDSS_INTR_MAX

 * All INTRs relevant for a specific target should be enabled via

 * _add_to_irq_offset_list()

 */

enum sde_intr_hwblk_type {

	SDE_INTR_HWBLK_TOP,

	SDE_INTR_HWBLK_INTF,

	SDE_INTR_HWBLK_AD4,

	SDE_INTR_HWBLK_INTF_TEAR,

	SDE_INTR_HWBLK_LTM,

	SDE_INTR_HWBLK_MAX

};



enum sde_intr_top_intr {

	SDE_INTR_TOP_INTR = 1,

	SDE_INTR_TOP_INTR2,

	SDE_INTR_TOP_HIST_INTR,

	SDE_INTR_TOP_MAX

};



struct sde_intr_irq_offsets {

	struct list_head list;

	enum sde_intr_hwblk_type type;

	u32 instance_idx;

	u32 base_offset;

};



/**
@@ -211,6 +212,7 @@ enum { 
 * @SDE_SSPP_BLOCK_SEC_UI    Blocks secure-ui layers

 * @SDE_SSPP_SCALER_QSEED3LITE Qseed3lite algorithm support

 * @SDE_SSPP_TRUE_INLINE_ROT_V1, Support of SSPP true inline rotation v1

 * @SDE_SSPP_INLINE_CONST_CLR Inline rotation requires const clr disabled

 * @SDE_SSPP_MAX             maximum value

 */

enum {
@@ -239,6 +241,7 @@ enum { 
	SDE_SSPP_BLOCK_SEC_UI,

	SDE_SSPP_SCALER_QSEED3LITE,

	SDE_SSPP_TRUE_INLINE_ROT_V1,

	SDE_SSPP_INLINE_CONST_CLR,

	SDE_SSPP_MAX

};
@@ -275,6 +278,7 @@ enum { 
 * @SDE_DISP_CWB_PREF         Layer mixer preferred for CWB

 * @SDE_DISP_PRIMARY_PREF     Layer mixer preferred for primary display

 * @SDE_DISP_SECONDARY_PREF   Layer mixer preferred for secondary display

 * @SDE_MIXER_COMBINED_ALPHA  Layer mixer bg and fg alpha in single register

 * @SDE_MIXER_MAX             maximum value

 */

enum {
@@ -285,6 +289,7 @@ enum { 
	SDE_DISP_PRIMARY_PREF,

	SDE_DISP_SECONDARY_PREF,

	SDE_DISP_CWB_PREF,

	SDE_MIXER_COMBINED_ALPHA,

	SDE_MIXER_MAX

};
@@ -459,11 +464,13 @@ enum { 
 * VBIF sub-blocks and features

 * @SDE_VBIF_QOS_OTLIM        VBIF supports OT Limit

 * @SDE_VBIF_QOS_REMAP        VBIF supports QoS priority remap

 * @SDE_VBIF_DISABLE_SHAREABLE: VBIF requires inner/outer shareables disabled

 * @SDE_VBIF_MAX              maximum value

 */

enum {

	SDE_VBIF_QOS_OTLIM = 0x1,

	SDE_VBIF_QOS_REMAP,

	SDE_VBIF_DISABLE_SHAREABLE,

	SDE_VBIF_MAX

};
@@ -947,12 +954,14 @@ struct sde_cdm_cfg { 
 * @type:              Interface type(DSI, DP, HDMI)

 * @controller_id:     Controller Instance ID in case of multiple of intf type

 * @prog_fetch_lines_worst_case	Worst case latency num lines needed to prefetch

 * @te_irq_offset:     Register offset for INTF TE IRQ block

 */

struct sde_intf_cfg  {

	SDE_HW_BLK_INFO;

	u32 type;   /* interface type*/

	u32 controller_id;

	u32 prog_fetch_lines_worst_case;

	u32 te_irq_offset;

};



/**
@@ -1272,6 +1281,9 @@ struct sde_limit_cfg { 
 * @has_3d_merge_reset Supports 3D merge reset

 * @has_decimation     Supports decimation

 * @has_qos_fl_nocalc  flag to indicate QoS fill level needs no calculation

 * @has_mixer_combined_alpha     Mixer has single register for FG & BG alpha

 * @vbif_disable_inner_outer_shareable     VBIF requires disabling shareables

 * @inline_disable_const_clr     Disable constant color during inline rotate

 * @sc_cfg: system cache configuration

 * @uidle_cfg		Settings for uidle feature

 * @sui_misr_supported  indicate if secure-ui-misr is supported
@@ -1287,7 +1299,7 @@ struct sde_limit_cfg { 
 * @has_cursor    indicates if hardware cursor is supported

 * @has_vig_p010  indicates if vig pipe supports p010 format

 * @inline_rot_formats	formats supported by the inline rotator feature

 * @mdss_irqs	  bitmap with the irqs supported by the target

 * @irq_offset_list     list of sde_intr_irq_offsets to initialize irq table

 */

struct sde_mdss_cfg {

	u32 hwversion;
@@ -1332,6 +1344,9 @@ struct sde_mdss_cfg { 
	bool has_3d_merge_reset;

	bool has_decimation;

	bool has_qos_fl_nocalc;

	bool has_mixer_combined_alpha;

	bool vbif_disable_inner_outer_shareable;

	bool inline_disable_const_clr;



	struct sde_sc_cfg sc_cfg;
@@ -1417,7 +1432,7 @@ struct sde_mdss_cfg { 
	struct sde_format_extended *virt_vig_formats;

	struct sde_format_extended *inline_rot_formats;



	DECLARE_BITMAP(mdss_irqs, MDSS_INTR_MAX);

	struct list_head irq_offset_list;

};



struct sde_mdss_hw_cfg_handler {
@@ -1471,6 +1486,22 @@ struct sde_mdss_cfg *sde_hw_catalog_init(struct drm_device *dev, u32 hw_rev); 
 */

void sde_hw_catalog_deinit(struct sde_mdss_cfg *sde_cfg);



/**

 * sde_hw_catalog_irq_offset_list_delete - delete the irq_offset_list

 *                                         maintained by the catalog

 * @head:      pointer to the catalog's irq_offset_list

 */

static inline void sde_hw_catalog_irq_offset_list_delete(

		struct list_head *head)

{

	struct sde_intr_irq_offsets *item, *tmp;



	list_for_each_entry_safe(item, tmp, head, list) {

		list_del(&item->list);

		kfree(item);

	}

}



/**

 * sde_hw_sspp_multirect_enabled - check multirect enabled for the sspp

 * @cfg:          pointer to sspp cfg
@@ -1481,9 +1512,4 @@ static inline bool sde_hw_sspp_multirect_enabled(const struct sde_sspp_cfg *cfg) 
			 test_bit(SDE_SSPP_SMART_DMA_V2, &cfg->features) ||

			 test_bit(SDE_SSPP_SMART_DMA_V2p5, &cfg->features);

}



static inline bool sde_hw_intf_te_supported(const struct sde_mdss_cfg *sde_cfg)

{

	return test_bit(SDE_INTF_TE, &(sde_cfg->intf[0].features));

}

#endif /* _SDE_HW_CATALOG_H */