Loading Makefile +1 −1 Original line number Diff line number Diff line VERSION = 3 PATCHLEVEL = 7 SUBLEVEL = 0 EXTRAVERSION = -rc6 EXTRAVERSION = -rc7 NAME = Terrified Chipmunk # *DOCUMENTATION* Loading arch/arm/boot/compressed/head.S +13 −1 Original line number Diff line number Diff line Loading @@ -652,6 +652,15 @@ __setup_mmu: sub r3, r4, #16384 @ Page directory size mov pc, lr ENDPROC(__setup_mmu) @ Enable unaligned access on v6, to allow better code generation @ for the decompressor C code: __armv6_mmu_cache_on: mrc p15, 0, r0, c1, c0, 0 @ read SCTLR bic r0, r0, #2 @ A (no unaligned access fault) orr r0, r0, #1 << 22 @ U (v6 unaligned access model) mcr p15, 0, r0, c1, c0, 0 @ write SCTLR b __armv4_mmu_cache_on __arm926ejs_mmu_cache_on: #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH mov r0, #4 @ put dcache in WT mode Loading Loading @@ -694,6 +703,9 @@ __armv7_mmu_cache_on: bic r0, r0, #1 << 28 @ clear SCTLR.TRE orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement orr r0, r0, #0x003c @ write buffer bic r0, r0, #2 @ A (no unaligned access fault) orr r0, r0, #1 << 22 @ U (v6 unaligned access model) @ (needed for ARM1176) #ifdef CONFIG_MMU #ifdef CONFIG_CPU_ENDIAN_BE8 orr r0, r0, #1 << 25 @ big-endian page tables Loading Loading @@ -914,7 +926,7 @@ proc_types: .word 0x0007b000 @ ARMv6 .word 0x000ff000 W(b) __armv4_mmu_cache_on W(b) __armv6_mmu_cache_on W(b) __armv4_mmu_cache_off W(b) __armv6_mmu_cache_flush Loading arch/arm/mm/proc-v6.S +1 −1 Original line number Diff line number Diff line Loading @@ -89,7 +89,7 @@ ENTRY(cpu_v6_dcache_clean_area) mov pc, lr /* * cpu_arm926_switch_mm(pgd_phys, tsk) * cpu_v6_switch_mm(pgd_phys, tsk) * * Set the translation table base pointer to be pgd_phys * Loading arch/mips/kernel/setup.c +20 −6 Original line number Diff line number Diff line Loading @@ -79,7 +79,7 @@ static struct resource data_resource = { .name = "Kernel data", }; void __init add_memory_region(phys_t start, phys_t size, long type) { int x = boot_mem_map.nr_map; struct boot_mem_map_entry *prev = boot_mem_map.map + x - 1; int i; /* Sanity check */ if (start + size < start) { Loading @@ -88,15 +88,29 @@ void __init add_memory_region(phys_t start, phys_t size, long type) } /* * Try to merge with previous entry if any. This is far less than * perfect but is sufficient for most real world cases. * Try to merge with existing entry, if any. */ if (x && prev->addr + prev->size == start && prev->type == type) { prev->size += size; for (i = 0; i < boot_mem_map.nr_map; i++) { struct boot_mem_map_entry *entry = boot_mem_map.map + i; unsigned long top; if (entry->type != type) continue; if (start + size < entry->addr) continue; /* no overlap */ if (entry->addr + entry->size < start) continue; /* no overlap */ top = max(entry->addr + entry->size, start + size); entry->addr = min(entry->addr, start); entry->size = top - entry->addr; return; } if (x == BOOT_MEM_MAP_MAX) { if (boot_mem_map.nr_map == BOOT_MEM_MAP_MAX) { pr_err("Ooops! Too many entries in the memory map!\n"); return; } Loading arch/mips/lib/mips-atomic.c +4 −4 Original line number Diff line number Diff line Loading @@ -56,7 +56,7 @@ __asm__( " .set pop \n" " .endm \n"); void arch_local_irq_disable(void) notrace void arch_local_irq_disable(void) { preempt_disable(); __asm__ __volatile__( Loading Loading @@ -93,7 +93,7 @@ __asm__( " .set pop \n" " .endm \n"); unsigned long arch_local_irq_save(void) notrace unsigned long arch_local_irq_save(void) { unsigned long flags; preempt_disable(); Loading Loading @@ -135,7 +135,7 @@ __asm__( " .set pop \n" " .endm \n"); void arch_local_irq_restore(unsigned long flags) notrace void arch_local_irq_restore(unsigned long flags) { unsigned long __tmp1; Loading @@ -159,7 +159,7 @@ void arch_local_irq_restore(unsigned long flags) EXPORT_SYMBOL(arch_local_irq_restore); void __arch_local_irq_restore(unsigned long flags) notrace void __arch_local_irq_restore(unsigned long flags) { unsigned long __tmp1; Loading Loading
Makefile +1 −1 Original line number Diff line number Diff line VERSION = 3 PATCHLEVEL = 7 SUBLEVEL = 0 EXTRAVERSION = -rc6 EXTRAVERSION = -rc7 NAME = Terrified Chipmunk # *DOCUMENTATION* Loading
arch/arm/boot/compressed/head.S +13 −1 Original line number Diff line number Diff line Loading @@ -652,6 +652,15 @@ __setup_mmu: sub r3, r4, #16384 @ Page directory size mov pc, lr ENDPROC(__setup_mmu) @ Enable unaligned access on v6, to allow better code generation @ for the decompressor C code: __armv6_mmu_cache_on: mrc p15, 0, r0, c1, c0, 0 @ read SCTLR bic r0, r0, #2 @ A (no unaligned access fault) orr r0, r0, #1 << 22 @ U (v6 unaligned access model) mcr p15, 0, r0, c1, c0, 0 @ write SCTLR b __armv4_mmu_cache_on __arm926ejs_mmu_cache_on: #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH mov r0, #4 @ put dcache in WT mode Loading Loading @@ -694,6 +703,9 @@ __armv7_mmu_cache_on: bic r0, r0, #1 << 28 @ clear SCTLR.TRE orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement orr r0, r0, #0x003c @ write buffer bic r0, r0, #2 @ A (no unaligned access fault) orr r0, r0, #1 << 22 @ U (v6 unaligned access model) @ (needed for ARM1176) #ifdef CONFIG_MMU #ifdef CONFIG_CPU_ENDIAN_BE8 orr r0, r0, #1 << 25 @ big-endian page tables Loading Loading @@ -914,7 +926,7 @@ proc_types: .word 0x0007b000 @ ARMv6 .word 0x000ff000 W(b) __armv4_mmu_cache_on W(b) __armv6_mmu_cache_on W(b) __armv4_mmu_cache_off W(b) __armv6_mmu_cache_flush Loading
arch/arm/mm/proc-v6.S +1 −1 Original line number Diff line number Diff line Loading @@ -89,7 +89,7 @@ ENTRY(cpu_v6_dcache_clean_area) mov pc, lr /* * cpu_arm926_switch_mm(pgd_phys, tsk) * cpu_v6_switch_mm(pgd_phys, tsk) * * Set the translation table base pointer to be pgd_phys * Loading
arch/mips/kernel/setup.c +20 −6 Original line number Diff line number Diff line Loading @@ -79,7 +79,7 @@ static struct resource data_resource = { .name = "Kernel data", }; void __init add_memory_region(phys_t start, phys_t size, long type) { int x = boot_mem_map.nr_map; struct boot_mem_map_entry *prev = boot_mem_map.map + x - 1; int i; /* Sanity check */ if (start + size < start) { Loading @@ -88,15 +88,29 @@ void __init add_memory_region(phys_t start, phys_t size, long type) } /* * Try to merge with previous entry if any. This is far less than * perfect but is sufficient for most real world cases. * Try to merge with existing entry, if any. */ if (x && prev->addr + prev->size == start && prev->type == type) { prev->size += size; for (i = 0; i < boot_mem_map.nr_map; i++) { struct boot_mem_map_entry *entry = boot_mem_map.map + i; unsigned long top; if (entry->type != type) continue; if (start + size < entry->addr) continue; /* no overlap */ if (entry->addr + entry->size < start) continue; /* no overlap */ top = max(entry->addr + entry->size, start + size); entry->addr = min(entry->addr, start); entry->size = top - entry->addr; return; } if (x == BOOT_MEM_MAP_MAX) { if (boot_mem_map.nr_map == BOOT_MEM_MAP_MAX) { pr_err("Ooops! Too many entries in the memory map!\n"); return; } Loading
arch/mips/lib/mips-atomic.c +4 −4 Original line number Diff line number Diff line Loading @@ -56,7 +56,7 @@ __asm__( " .set pop \n" " .endm \n"); void arch_local_irq_disable(void) notrace void arch_local_irq_disable(void) { preempt_disable(); __asm__ __volatile__( Loading Loading @@ -93,7 +93,7 @@ __asm__( " .set pop \n" " .endm \n"); unsigned long arch_local_irq_save(void) notrace unsigned long arch_local_irq_save(void) { unsigned long flags; preempt_disable(); Loading Loading @@ -135,7 +135,7 @@ __asm__( " .set pop \n" " .endm \n"); void arch_local_irq_restore(unsigned long flags) notrace void arch_local_irq_restore(unsigned long flags) { unsigned long __tmp1; Loading @@ -159,7 +159,7 @@ void arch_local_irq_restore(unsigned long flags) EXPORT_SYMBOL(arch_local_irq_restore); void __arch_local_irq_restore(unsigned long flags) notrace void __arch_local_irq_restore(unsigned long flags) { unsigned long __tmp1; Loading