Merge branch 'perfcounters-for-linus' of... (8a1ca8ce) · Commits · e / devices / android_kernel_fairphone_FP5

MAINTAINERS

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Original line number	Diff line number	Diff line
		@@ -4403,6 +4403,16 @@ S: Maintained
		F: include/linux/delayacct.h
		F: kernel/delayacct.c

		PERFORMANCE COUNTER SUBSYSTEM
		P: Peter Zijlstra
		M: a.p.zijlstra@chello.nl
		P: Paul Mackerras
		M: paulus@samba.org
		P: Ingo Molnar
		M: mingo@elte.hu
		L: linux-kernel@vger.kernel.org
		S: Supported

		PERSONALITY HANDLING
		P: Christoph Hellwig
		M: hch@infradead.org

arch/powerpc/include/asm/hw_irq.h

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		@@ -131,5 +131,44 @@ static inline int irqs_disabled_flags(unsigned long flags)
		*/
		struct irq_chip;

		#ifdef CONFIG_PERF_COUNTERS
		static inline unsigned long test_perf_counter_pending(void)
		{
		unsigned long x;

		asm volatile("lbz %0,%1(13)"
		: "=r" (x)
		: "i" (offsetof(struct paca_struct, perf_counter_pending)));
		return x;
		}

		static inline void set_perf_counter_pending(void)
		{
		asm volatile("stb %0,%1(13)" : :
		"r" (1),
		"i" (offsetof(struct paca_struct, perf_counter_pending)));
		}

		static inline void clear_perf_counter_pending(void)
		{
		asm volatile("stb %0,%1(13)" : :
		"r" (0),
		"i" (offsetof(struct paca_struct, perf_counter_pending)));
		}

		extern void perf_counter_do_pending(void);

		#else

		static inline unsigned long test_perf_counter_pending(void)
		{
		return 0;
		}

		static inline void set_perf_counter_pending(void) {}
		static inline void clear_perf_counter_pending(void) {}
		static inline void perf_counter_do_pending(void) {}
		#endif /* CONFIG_PERF_COUNTERS */

		#endif /* __KERNEL__ */
		#endif /* _ASM_POWERPC_HW_IRQ_H */

arch/powerpc/include/asm/paca.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -99,6 +99,7 @@ struct paca_struct {
		u8 soft_enabled; /* irq soft-enable flag */
		u8 hard_enabled; /* set if irqs are enabled in MSR */
		u8 io_sync; /* writel() needs spin_unlock sync */
		u8 perf_counter_pending; /* PM interrupt while soft-disabled */

		/* Stuff for accurate time accounting */
		u64 user_time; /* accumulated usermode TB ticks */

arch/powerpc/include/asm/perf_counter.h

0 → 100644

+98 −0

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		/*
		* Performance counter support - PowerPC-specific definitions.
		*
		* Copyright 2008-2009 Paul Mackerras, IBM Corporation.
		*
		* This program is free software; you can redistribute it and/or
		* modify it under the terms of the GNU General Public License
		* as published by the Free Software Foundation; either version
		* 2 of the License, or (at your option) any later version.
		*/
		#include <linux/types.h>

		#define MAX_HWCOUNTERS 8
		#define MAX_EVENT_ALTERNATIVES 8
		#define MAX_LIMITED_HWCOUNTERS 2

		/*
		* This struct provides the constants and functions needed to
		* describe the PMU on a particular POWER-family CPU.
		*/
		struct power_pmu {
		int n_counter;
		int max_alternatives;
		u64 add_fields;
		u64 test_adder;
		int (*compute_mmcr)(u64 events[], int n_ev,
		unsigned int hwc[], u64 mmcr[]);
		int (get_constraint)(u64 event, u64 mskp, u64 *valp);
		int (*get_alternatives)(u64 event, unsigned int flags,
		u64 alt[]);
		void (*disable_pmc)(unsigned int pmc, u64 mmcr[]);
		int (*limited_pmc_event)(u64 event);
		u32 flags;
		int n_generic;
		int *generic_events;
		int (*cache_events)[PERF_COUNT_HW_CACHE_MAX]
		[PERF_COUNT_HW_CACHE_OP_MAX]
		[PERF_COUNT_HW_CACHE_RESULT_MAX];
		};

		extern struct power_pmu *ppmu;

		/*
		* Values for power_pmu.flags
		*/
		#define PPMU_LIMITED_PMC5_6 1 /* PMC5/6 have limited function */
		#define PPMU_ALT_SIPR 2 /* uses alternate posn for SIPR/HV */

		/*
		* Values for flags to get_alternatives()
		*/
		#define PPMU_LIMITED_PMC_OK 1 /* can put this on a limited PMC */
		#define PPMU_LIMITED_PMC_REQD 2 /* have to put this on a limited PMC */
		#define PPMU_ONLY_COUNT_RUN 4 /* only counting in run state */

		struct pt_regs;
		extern unsigned long perf_misc_flags(struct pt_regs *regs);
		#define perf_misc_flags(regs) perf_misc_flags(regs)

		extern unsigned long perf_instruction_pointer(struct pt_regs *regs);

		/*
		* The power_pmu.get_constraint function returns a 64-bit value and
		* a 64-bit mask that express the constraints between this event and
		* other events.
		*
		* The value and mask are divided up into (non-overlapping) bitfields
		* of three different types:
		*
		* Select field: this expresses the constraint that some set of bits
		* in MMCR* needs to be set to a specific value for this event. For a
		* select field, the mask contains 1s in every bit of the field, and
		* the value contains a unique value for each possible setting of the
		* MMCR* bits. The constraint checking code will ensure that two events
		* that set the same field in their masks have the same value in their
		* value dwords.
		*
		* Add field: this expresses the constraint that there can be at most
		* N events in a particular class. A field of k bits can be used for
		* N <= 2^(k-1) - 1. The mask has the most significant bit of the field
		* set (and the other bits 0), and the value has only the least significant
		* bit of the field set. In addition, the 'add_fields' and 'test_adder'
		* in the struct power_pmu for this processor come into play. The
		* add_fields value contains 1 in the LSB of the field, and the
		* test_adder contains 2^(k-1) - 1 - N in the field.
		*
		* NAND field: this expresses the constraint that you may not have events
		* in all of a set of classes. (For example, on PPC970, you can't select
		* events from the FPU, ISU and IDU simultaneously, although any two are
		* possible.) For N classes, the field is N+1 bits wide, and each class
		* is assigned one bit from the least-significant N bits. The mask has
		* only the most-significant bit set, and the value has only the bit
		* for the event's class set. The test_adder has the least significant
		* bit set in the field.
		*
		* If an event is not subject to the constraint expressed by a particular
		* field, then it will have 0 in both the mask and value for that field.
		*/

arch/powerpc/include/asm/reg.h

+2 −0

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		@@ -492,11 +492,13 @@
		#define MMCR0_FCHV 0x00000001UL /* freeze conditions in hypervisor mode */
		#define SPRN_MMCR1 798
		#define SPRN_MMCRA 0x312
		#define MMCRA_SDSYNC 0x80000000UL /* SDAR synced with SIAR */
		#define MMCRA_SIHV 0x10000000UL /* state of MSR HV when SIAR set */
		#define MMCRA_SIPR 0x08000000UL /* state of MSR PR when SIAR set */
		#define MMCRA_SLOT 0x07000000UL /* SLOT bits (37-39) */
		#define MMCRA_SLOT_SHIFT 24
		#define MMCRA_SAMPLE_ENABLE 0x00000001UL /* enable sampling */
		#define POWER6_MMCRA_SDSYNC 0x0000080000000000ULL /* SDAR/SIAR synced */
		#define POWER6_MMCRA_SIHV 0x0000040000000000ULL
		#define POWER6_MMCRA_SIPR 0x0000020000000000ULL
		#define POWER6_MMCRA_THRM 0x00000020UL