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Commit 899f0e66 authored by Gerlando Falauto's avatar Gerlando Falauto Committed by Thomas Gleixner
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genirq: Generic chip: Add support for per chip type mask cache 



Today the same interrupt mask cache (stored within struct irq_chip_generic)
is shared between all the irq_chip_type instances. As there are instances
where each irq_chip_type uses a distinct mask register (as it is the case
for Orion SoCs), sharing a single mask cache may be incorrect.
So add a distinct pointer for each irq_chip_type, which for now
points to the original mask register within irq_chip_generic.
So no functional changes here.

[ tglx: Minor cosmetic tweaks ]

Reported-by: default avatarJoey Oravec <joravec@drewtech.com>
Signed-off-by: default avatarSimon Guinot <sguinot@lacie.com>
Signed-off-by: default avatarHolger Brunck <holger.brunck@keymile.com>
Signed-off-by: default avatarGerlando Falauto <gerlando.falauto@keymile.com>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Lennert Buytenhek <kernel@wantstofly.org>
Cc: Russell King - ARM Linux <linux@arm.linux.org.uk>
Cc: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Cc: Holger Brunck <Holger.Brunck@keymile.com>
Cc: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Acked-by: default avatarGrant Likely <grant.likely@linaro.org>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: devicetree-discuss@lists.ozlabs.org
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Ben Dooks <ben-linux@fluff.org>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Simon Guinot <simon@sequanux.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Jean-Francois Moine <moinejf@free.fr>
Cc: Nicolas Pitre <nico@fluxnic.net>
Cc: Rob Landley <rob@landley.net>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Link: http://lkml.kernel.org/r/20130506142539.082226607@linutronix.de


Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
parent cfeaa93f

include/linux/irq.h

+5 −1
Original line number Original line Diff line number Diff line
@@ -644,6 +644,8 @@ struct irq_chip_regs { 
 * @regs:		Register offsets for this chip

 * @regs:		Register offsets for this chip

 * @handler:		Flow handler associated with this chip

 * @handler:		Flow handler associated with this chip

 * @type:		Chip can handle these flow types

 * @type:		Chip can handle these flow types

 * @mask_cache_priv:	Cached mask register private to the chip type

 * @mask_cache:		Pointer to cached mask register

 *

 *

 * A irq_generic_chip can have several instances of irq_chip_type when

 * A irq_generic_chip can have several instances of irq_chip_type when

 * it requires different functions and register offsets for different

 * it requires different functions and register offsets for different
@@ -654,6 +656,8 @@ struct irq_chip_type { 
	struct irq_chip_regs	regs;

	struct irq_chip_regs	regs;

	irq_flow_handler_t	handler;

	irq_flow_handler_t	handler;

	u32			type;

	u32			type;

	u32			mask_cache_priv;

	u32			*mask_cache;

};

};





/**

/**
@@ -662,7 +666,7 @@ struct irq_chip_type { 
 * @reg_base:		Register base address (virtual)

 * @reg_base:		Register base address (virtual)

 * @irq_base:		Interrupt base nr for this chip

 * @irq_base:		Interrupt base nr for this chip

 * @irq_cnt:		Number of interrupts handled by this chip

 * @irq_cnt:		Number of interrupts handled by this chip

 * @mask_cache:		Cached mask register

 * @mask_cache:		Cached mask register shared between all chip types

 * @type_cache:		Cached type register

 * @type_cache:		Cached type register

 * @polarity_cache:	Cached polarity register

 * @polarity_cache:	Cached polarity register

 * @wake_enabled:	Interrupt can wakeup from suspend

 * @wake_enabled:	Interrupt can wakeup from suspend

kernel/irq/generic-chip.c

+10 −6
Original line number Original line Diff line number Diff line
@@ -39,7 +39,7 @@ void irq_gc_mask_disable_reg(struct irq_data *d) 




	irq_gc_lock(gc);

	irq_gc_lock(gc);

	irq_reg_writel(mask, gc->reg_base + ct->regs.disable);

	irq_reg_writel(mask, gc->reg_base + ct->regs.disable);

	gc->mask_cache &= ~mask;

	*ct->mask_cache &= ~mask;

	irq_gc_unlock(gc);

	irq_gc_unlock(gc);

}

}
@@ -57,8 +57,8 @@ void irq_gc_mask_set_bit(struct irq_data *d) 
	u32 mask = 1 << (d->irq - gc->irq_base);

	u32 mask = 1 << (d->irq - gc->irq_base);





	irq_gc_lock(gc);

	irq_gc_lock(gc);

	gc->mask_cache |= mask;

	*ct->mask_cache |= mask;

	irq_reg_writel(gc->mask_cache, gc->reg_base + ct->regs.mask);

	irq_reg_writel(*ct->mask_cache, gc->reg_base + ct->regs.mask);

	irq_gc_unlock(gc);

	irq_gc_unlock(gc);

}

}
@@ -76,8 +76,8 @@ void irq_gc_mask_clr_bit(struct irq_data *d) 
	u32 mask = 1 << (d->irq - gc->irq_base);

	u32 mask = 1 << (d->irq - gc->irq_base);





	irq_gc_lock(gc);

	irq_gc_lock(gc);

	gc->mask_cache &= ~mask;

	*ct->mask_cache &= ~mask;

	irq_reg_writel(gc->mask_cache, gc->reg_base + ct->regs.mask);

	irq_reg_writel(*ct->mask_cache, gc->reg_base + ct->regs.mask);

	irq_gc_unlock(gc);

	irq_gc_unlock(gc);

}

}
@@ -96,7 +96,7 @@ void irq_gc_unmask_enable_reg(struct irq_data *d) 




	irq_gc_lock(gc);

	irq_gc_lock(gc);

	irq_reg_writel(mask, gc->reg_base + ct->regs.enable);

	irq_reg_writel(mask, gc->reg_base + ct->regs.enable);

	gc->mask_cache |= mask;

	*ct->mask_cache |= mask;

	irq_gc_unlock(gc);

	irq_gc_unlock(gc);

}

}
@@ -250,6 +250,10 @@ void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk, 
	if (flags & IRQ_GC_INIT_MASK_CACHE)

	if (flags & IRQ_GC_INIT_MASK_CACHE)

		gc->mask_cache = irq_reg_readl(gc->reg_base + ct->regs.mask);

		gc->mask_cache = irq_reg_readl(gc->reg_base + ct->regs.mask);





	/* Initialize mask cache pointer */

	for (i = 0; i < gc->num_ct; i++)

		ct[i].mask_cache = &gc->mask_cache;



	for (i = gc->irq_base; msk; msk >>= 1, i++) {

	for (i = gc->irq_base; msk; msk >>= 1, i++) {

		if (!(msk & 0x01))

		if (!(msk & 0x01))

			continue;

			continue;