Merge "dt-bindings: kgsl: Add device tree bindings for the KGSL GPU driver"

Adreno bus monitor device

kgsl-busmon is a psedo device that represents a devfreq bus bandwidth

governor. If this device is present then two different governors are used

for GPU DCVS and bus DCVS.

Required properties:

- compatible:	Must be "qcom,kgsl-busmon"

- label:	Device name used for sysfs entry.

Example:

qcom,kgsl-busmon {

	compatible = "qcom,kgsl-busmon";

	label = "kgsl-busmon";

};

Qualcomm Technologies, Inc. GPU Graphics Management Unit (GMU)

Required properties:

- compatible :

	- "qcom,gpu-gmu"

	- "qcom,gpu-rgmu"

- reg:		Specifies the GMU register base address and size.

- reg-names:		Resource names used for the physical address

		and length of GMU registers.

- interrupts:	Interrupt mapping for GMU and HFI IRQs.

- interrupt-names:	String property to describe the name of each interrupt.

Bus Scaling Data:

qcom,msm-bus,name: String property to describe the name of bus client.

qcom,msm-bus,num-cases: This is the the number of Bus Scaling use cases defined in the vectors property.

qcom,msm-bus,num-paths: This represents the number of paths in each Bus Scaling Usecase.

qcom,msm-bus,vectors-KBps: A series of 4 cell properties, format of which is:

		<src dst ab ib>, <src dst ab ib>, // For Bus Scaling Usecase 1

		<src dst ab ib>, <src dst ab ib>, // For Bus Scaling Usecase 2

		<..  ..  .. ..>, <..  ..  .. ..>; // For Bus Scaling Usecase n

		This property is a series of all vectors for all Bus Scaling Usecases.

		Each set of vectors for each usecase describes bandwidth votes for a combination

		of src/dst ports.  The driver will set the desired use case based on the selected

		power level and the desired bandwidth vote will be registered for the port pairs.

GMU GDSC/regulators:

- regulator-names:	List of regulator name strings

- vddcx-supply:		Phandle for vddcx regulator device node.

- vdd-supply:		Phandle for vdd regulator device node.

- clock:	List of clocks to be used for GMU register access and DCVS. See

		  Documentation/devicetree/bindings/clock/clock-bindings.txt

		  for information about the format. For each clock specified

		  here, there must be a corresponding entry in clock-names

		  (see below).

- clock-names:	List of clock names corresponding to the clocks specified in

		  the "clocks" property (above). See

		  Documentation/devicetree/bindings/clock/clock-bindings.txt

		  for more info. Currently GMU required these clock names:

			"gmu_clk", "ahb_clk", "cxo_clk", "axi_clk", "memnoc_clk",

			"rbcpr_clk"

- List of sub nodes, one for each of the translation context banks needed

		for GMU to access system memory in different operating mode. Currently

		supported names are:

		- gmu_user: used for GMU 'user' mode address space.

		- gmu_kernel: used for GMU 'kernel' mode address space.

		Each sub node has the following required properties:

		- compatible : "qcom,smmu-gmu-user-cb" or "qcom,smmu-gmu-kernel-cb"

		- iommus : Specifies the SID's used by this context bank, this

			needs to be <kgsl_smmu SID> pair, kgsl_smmu is the string

			parsed by iommu driver to match this context bank with the

			kgsl_smmu device defined in iommu device tree. On targets

			where the msm iommu driver is used rather than the arm smmu

			driver, this property may be absent.

Example:

gmu: qcom,gmu@2c6a000 {

	label = "kgsl-gmu";

	compatible = "qcom,gpu-gmu";

	reg = <0x2c6a000 0x30000>;

	reg-names = "kgsl_gmu_reg";

	interrupts = <0 304 0>, <0 305 0>;

	interrupt-names = "kgsl_gmu_irq", "kgsl_hfi_irq";

	qcom,msm-bus,name = "cnoc";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

			<26 10036 0 0>,		// CNOC off

			<26 10036 0 100>;	// CNOC on

	regulator-name = "vddcx", "vdd";

	vddcx-supply = <&gpu_cx_gdsc>;

	vdd-supply = <&gpu_gx_gdsc>;

	clocks = <&clock_gpugcc clk_gcc_gmu_clk>,

		<&clock_gcc GCC_GPU_CFG_AHB_CLK>,

		<&clock_gpucc GPU_CC_CXO_CLK>,

		<&clock_gcc GCC_DDRSS_GPU_AXI_CLK>,

		<&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>,

		<&clock_gpucc GPU_CC_RBCPR_CLK>;

	clock-names = "gmu_clk", "ahb_clk", "cxo_clk",

				"axi_clk", "memnoc_clk", "rbcpr_clk";

	gmu_user: gmu_user {

	      compatible = "qcom,smmu-gmu-user-cb";

	      iommus = <&kgsl_smmu 4>;

	};

	gmu_kernel: gmu_kernel {

	      compatible = "qcom,smmu-gmu-kernel-cb";

	      iommus = <&kgsl_smmu 5>;

	};

};

Qualcomm Technologies, Inc. GPU IOMMU

Required properties:

Required properties:

- compatible : one of:

	- "qcom,kgsl-smmu-v1"

	- "qcom,kgsl-smmu-v2"

- reg		: Base address and size of the SMMU.

- clocks	: List of clocks to be used during SMMU register access. See

		  Documentation/devicetree/bindings/clock/clock-bindings.txt

		  for information about the format. For each clock specified

		  here, there must be a corresponding entry in clock-names

		  (see below).

- clock-names	: List of clock names corresponding to the clocks specified in

		  the "clocks" property (above). See

		  Documentation/devicetree/bindings/clock/clock-bindings.txt

		  for more info.

- qcom,protect  : The GPU register region which must be protected by a CP

		  protected mode. On some targets this region must cover

		  the entire SMMU register space, on others there

		  is a separate aperture for CP to program context banks.

Optional properties:

- qcom,retention :  A boolean specifying if retention is supported on this target

- qcom,global_pt :  A boolean specifying if global pagetable should be used.

		  When not set we use per process pagetables

- qcom,hyp_secure_alloc : A bool specifying if the hypervisor is used on this target

		  for secure buffer allocation

- List of sub nodes, one for each of the translation context banks supported.

  The driver uses the names of these nodes to determine how they are used,

  currently supported names are:

  - gfx3d_user : Used for the 'normal' GPU address space.

  - gfx3d_secure : Used for the content protection address space.

  - gfx3d_secure_alt : Used for the content protection address space for alternative SID.

  Each sub node has the following required properties:

	- compatible : "qcom,smmu-kgsl-cb"

	- iommus : Specifies the SID's used by this context bank, this needs to be

		   <kgsl_smmu SID> pair, kgsl_smmu is the string parsed by iommu

		   driver to match this context bank with the kgsl_smmu device

		   defined in iommu device tree. On targets where the msm iommu

		   driver is used rather than the arm smmu driver, this property

		   may be absent.

Example:

msm_iommu: qcom,kgsl-iommu@2ca0000 {

	compatible = "qcom,kgsl-smmu-v2";

	reg = <0x2ca0000 0x10000>;

	qcom,protect = <0xa0000 0xc000>;

	clocks = <&clock_mmss clk_gpu_ahb_clk>,

		<&clock_gcc clk_gcc_mmss_bimc_gfx_clk>,

		<&clock_mmss clk_mmss_mmagic_ahb_clk>,

		<&clock_mmss clk_mmss_mmagic_cfg_ahb_clk>;

	clock-names = "gpu_ahb_clk", "bimc_gfx_clk", "mmagic_ahb_clk", "mmagic_cfg_ahb_clk";

	qcom,secure_align_mask = <0xfff>;

	qcom,retention;

	qcom,global_pt;

	gfx3d_user: gfx3d_user {

		compatible = "qcom,smmu-kgsl-cb";

		iommus = <&kgsl_smmu 0>,

			 <&kgsl_smmu 1>;

	};

	gfx3d_secure: gfx3d_secure {

		compatible = "qcom,smmu-kgsl-cb";

		iommus = <&kgsl_smmu 2>;

	};

	gfx3d_secure_alt: gfx3d_secure_alt {

		compatible = "qcom,smmu-kgsl-cb";

		iommus = <&kgsl_smmu 2>, <&kgsl_smmu 1>;

	};

};

Qualcomm Technologies, Inc. GPU powerlevels

Powerlevels are defined in sets by qcom,gpu-pwrlevels. Multiple sets (bins)

can be defined within qcom,gpu-pwrelvel-bins. Each powerlevel defines a

voltage, bus, bandwidth level, and a DVM value.

- qcom,gpu-pwrlevel-bins:	Contains one or more qcom,gpu-pwrlevels sets

Properties:

- compatible:			Must be qcom,gpu-pwrlevel-bins

- qcom,gpu-pwrlevels:		Defines a set of powerlevels

Properties:

- qcom,speed-bin:		Speed bin identifier for the set - must match

				the value read from the hardware

- qcom,initial-pwrlevel:	GPU wakeup powerlevel

- qcom,gpu-pwrlevel:		A single powerlevel

- qcom,ca-target-pwrlevel:

				This value indicates which qcom,gpu-pwrlevel

				to jump on in case of context aware power level

				jump.

Required Properties:

- reg:				Index of the powerlevel (0 = highest perf)

- qcom,gpu-freq			GPU frequency for the powerlevel (in Hz)

- qcom,bus-freq			Index to a bus level (defined by the bus

				settings).

- qcom,bus-freq-ddrX		If specified, define the DDR specific bus

				frequency for the power level.  X will be the

				return value from of_fdt_get_ddrtype().

Optional Properties:

- qcom,bus-min			Minimum bus level to set for the power level

- qcom,bus-min-ddrX		If specified, define the DDR specific minimum

				bus level for the power level.  X will be the

				return value from of_fdt_get_ddrtype().

- qcom,bus-max			maximum bus level to set for the power level

- qcom,bus-max-ddrX		If specified, define the DDR specific maximum

				bus level for the power level.  X will be the

				return value from of_fdt_get_ddrtype().

- qcom,acd-level:		Value that is used as a register setting for

				the ACD power feature. It helps to determine

				the threshold for when ACD activates. Zero is

				the default value, and the setting where ACD

				will never activate.

Example:

qcom,gpu-pwrlevel@6 {

	reg = <6>;

	qcom,gpu-freq = <0>;

	qcom,bus-freq = <0>;

	qcom,bus-min = <0>;

	qcom,bus-max = <0>;

	qcom,acd-level = <0xffffffff>;

};

Example for DDR4/DDR5 specific part:

qcom,gpu-pwrlevel@6 {

	reg = <6>;

	qcom,gpu-freq = <480000000>;

	/* DDR5 */

	qcom,bus-freq-ddr8 = <10>;

	qcom,bus-min-ddr8 = <9>;

	qcom,bus-max-ddr8 = <11>;

	/* DDR 4 */

	qcom,bus-freq-ddr7 = <9>;

	qcom,bus-min-ddr7 = <7>;

	qcom,bus-max-ddr7 = <9>;

	qcom,acd-level = <0xffffffff>;

};