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Commit 897e1dde authored by Andrew Chew's avatar Andrew Chew Committed by Peter De Schrijver
Browse files

clk: tegra: Set the clk parent of host1x to pll_p 



The power-on default parent for this clock is pll_m, which turns out to
be wrong. Previously, bootloader reparented this clock.  We'll do it in
the kernel as well, so that there's one less thing that we depend on
bootloader to initialize.

Signed-off-by: default avatarAndrew Chew <achew@nvidia.com>
Signed-off-by: default avatarMark Zhang <markz@nvidia.com>
parent 252d0d2b

drivers/clk/tegra/clk-tegra114.c

+1 −0
Original line number Diff line number Diff line
@@ -2183,6 +2183,7 @@ static struct tegra_clk_init_table init_table[] __initdata = { 
	{TEGRA114_CLK_I2S2, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0},

	{TEGRA114_CLK_I2S3, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0},

	{TEGRA114_CLK_I2S4, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0},

	{TEGRA114_CLK_HOST1X, TEGRA114_CLK_PLL_P, 136000000, 0},

	{TEGRA114_CLK_DFLL_SOC, TEGRA114_CLK_PLL_P, 51000000, 1},

	{TEGRA114_CLK_DFLL_REF, TEGRA114_CLK_PLL_P, 51000000, 1},

	{TEGRA114_CLK_GR_2D, TEGRA114_CLK_PLL_C2, 300000000, 0},