Loading qcom/holi.dtsi +262 −0 Original line number Diff line number Diff line Loading @@ -3,6 +3,7 @@ #include <dt-bindings/clock/qcom,gpucc-holi.h> #include <dt-bindings/clock/qcom,rpmcc.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/soc/qcom,ipcc.h> / { model = "Qualcomm Technologies, Inc. Holi"; Loading Loading @@ -533,6 +534,267 @@ #clock-cells = <1>; #reset-cells = <1>; }; tcsr_mutex_block: syscon@340000 { compatible = "syscon"; reg = <0x340000 0x20000>; }; tcsr_mutex: hwlock { compatible = "qcom,tcsr-mutex"; syscon = <&tcsr_mutex_block 0 0x1000>; #hwlock-cells = <1>; }; smem: qcom,smem { compatible = "qcom,smem"; memory-region = <&smem_mem>; hwlocks = <&tcsr_mutex 3>; }; qcom,smp2p-adsp { compatible = "qcom,smp2p"; qcom,smem = <443>, <429>; interrupt-parent = <&ipcc_mproc>; interrupts = <IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P IRQ_TYPE_EDGE_RISING>; mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P>; qcom,local-pid = <0>; qcom,remote-pid = <2>; adsp_smp2p_out: master-kernel { qcom,entry-name = "master-kernel"; #qcom,smem-state-cells = <1>; }; adsp_smp2p_in: slave-kernel { qcom,entry-name = "slave-kernel"; interrupt-controller; #interrupt-cells = <2>; }; }; qcom,smp2p-modem { compatible = "qcom,smp2p"; qcom,smem = <435>, <428>; interrupt-parent = <&ipcc_mproc>; interrupts = <IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P IRQ_TYPE_EDGE_RISING>; mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P>; qcom,local-pid = <0>; qcom,remote-pid = <1>; modem_smp2p_out: master-kernel { qcom,entry-name = "master-kernel"; #qcom,smem-state-cells = <1>; }; modem_smp2p_in: slave-kernel { qcom,entry-name = "slave-kernel"; interrupt-controller; #interrupt-cells = <2>; }; smp2p_ipa_1_out: qcom,smp2p-ipa-1-out { qcom,entry-name = "ipa"; #qcom,smem-state-cells = <1>; }; /* ipa - inbound entry from mss */ smp2p_ipa_1_in: qcom,smp2p-ipa-1-in { qcom,entry-name = "ipa"; interrupt-controller; #interrupt-cells = <2>; }; }; qcom,smp2p-cdsp { compatible = "qcom,smp2p"; qcom,smem = <94>, <432>; interrupt-parent = <&ipcc_mproc>; interrupts = <IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P IRQ_TYPE_EDGE_RISING>; mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>; qcom,local-pid = <0>; qcom,remote-pid = <5>; cdsp_smp2p_out: master-kernel { qcom,entry-name = "master-kernel"; #qcom,smem-state-cells = <1>; }; cdsp_smp2p_in: slave-kernel { qcom,entry-name = "slave-kernel"; interrupt-controller; #interrupt-cells = <2>; }; }; rpm_msg_ram: memory@045f0000 { compatible = "qcom,rpm-msg-ram"; reg = <0x45f0000 0x7000>; }; rpm-glink { compatible = "qcom,glink-rpm"; qcom,rpm-msg-ram = <&rpm_msg_ram>; mboxes = <&ipcc_mproc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; mbox-names = "rpm_smem"; interrupt-parent = <&ipcc_mproc>; interrupts = <IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; qcom,rpm_glink_ssr { qcom,glink-channels = "glink_ssr"; qcom,notify-edges = <&glink_modem>, <&glink_adsp>, <&glink_cdsp>; }; }; qcom,glink { compatible = "qcom,glink"; #address-cells = <1>; #size-cells = <1>; ranges; glink_modem: modem { qcom,remote-pid = <1>; transport = "smem"; mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_GLINK_QMP>; mbox-names = "mpss_smem"; interrupt-parent = <&ipcc_mproc>; interrupts = <IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; label = "modem"; qcom,glink-label = "mpss"; qcom,modem_qrtr { qcom,glink-channels = "IPCRTR"; qcom,low-latency; qcom,intents = <0x800 5 0x2000 3 0x4400 2>; }; qcom,modem_ds { qcom,glink-channels = "DS"; qcom,intents = <0x4000 0x2>; }; qcom,modem_glink_ssr { qcom,glink-channels = "glink_ssr"; qcom,notify-edges = <&glink_adsp>; }; }; glink_adsp: adsp { qcom,remote-pid = <2>; transport = "smem"; mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_GLINK_QMP>; mbox-names = "adsp_smem"; interrupt-parent = <&ipcc_mproc>; interrupts = <IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; label = "adsp"; qcom,glink-label = "lpass"; qcom,adsp_qrtr { qcom,glink-channels = "IPCRTR"; qcom,intents = <0x800 5 0x2000 3 0x4400 2>; }; qcom,adsp_glink_ssr { qcom,glink-channels = "glink_ssr"; qcom,notify-edges = <&glink_modem>; }; qcom,pmic_glink_rpmsg { qcom,glink-channels = "PMIC_RTR_ADSP_APPS"; }; qcom,pmic_glink_log_rpmsg { qcom,glink-channels = "PMIC_LOGS_ADSP_APPS"; qcom,intents = <0x800 5 0xc00 3>; }; }; glink_cdsp: cdsp { qcom,remote-pid = <5>; transport = "smem"; mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_GLINK_QMP>; mbox-names = "dsps_smem"; interrupt-parent = <&ipcc_mproc>; interrupts = <IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; label = "cdsp"; qcom,glink-label = "cdsp"; qcom,cdsp_qrtr { qcom,glink-channels = "IPCRTR"; qcom,intents = <0x800 5 0x2000 3 0x4400 2>; }; }; }; qcom,glinkpkt { compatible = "qcom,glinkpkt"; qcom,glinkpkt-at-mdm0 { qcom,glinkpkt-edge = "mpss"; qcom,glinkpkt-ch-name = "DS"; qcom,glinkpkt-dev-name = "at_mdm0"; }; qcom,glinkpkt-apr-apps2 { qcom,glinkpkt-edge = "adsp"; qcom,glinkpkt-ch-name = "apr_apps2"; qcom,glinkpkt-dev-name = "apr_apps2"; }; qcom,glinkpkt-data40-cntl { qcom,glinkpkt-edge = "mpss"; qcom,glinkpkt-ch-name = "DATA40_CNTL"; qcom,glinkpkt-dev-name = "smdcntl8"; }; qcom,glinkpkt-data1 { qcom,glinkpkt-edge = "mpss"; qcom,glinkpkt-ch-name = "DATA1"; qcom,glinkpkt-dev-name = "smd7"; }; qcom,glinkpkt-data4 { qcom,glinkpkt-edge = "mpss"; qcom,glinkpkt-ch-name = "DATA4"; qcom,glinkpkt-dev-name = "smd8"; }; qcom,glinkpkt-data11 { qcom,glinkpkt-edge = "mpss"; qcom,glinkpkt-ch-name = "DATA11"; qcom,glinkpkt-dev-name = "smd11"; }; }; }; #include "holi-pinctrl.dtsi" Loading Loading
qcom/holi.dtsi +262 −0 Original line number Diff line number Diff line Loading @@ -3,6 +3,7 @@ #include <dt-bindings/clock/qcom,gpucc-holi.h> #include <dt-bindings/clock/qcom,rpmcc.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/soc/qcom,ipcc.h> / { model = "Qualcomm Technologies, Inc. Holi"; Loading Loading @@ -533,6 +534,267 @@ #clock-cells = <1>; #reset-cells = <1>; }; tcsr_mutex_block: syscon@340000 { compatible = "syscon"; reg = <0x340000 0x20000>; }; tcsr_mutex: hwlock { compatible = "qcom,tcsr-mutex"; syscon = <&tcsr_mutex_block 0 0x1000>; #hwlock-cells = <1>; }; smem: qcom,smem { compatible = "qcom,smem"; memory-region = <&smem_mem>; hwlocks = <&tcsr_mutex 3>; }; qcom,smp2p-adsp { compatible = "qcom,smp2p"; qcom,smem = <443>, <429>; interrupt-parent = <&ipcc_mproc>; interrupts = <IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P IRQ_TYPE_EDGE_RISING>; mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P>; qcom,local-pid = <0>; qcom,remote-pid = <2>; adsp_smp2p_out: master-kernel { qcom,entry-name = "master-kernel"; #qcom,smem-state-cells = <1>; }; adsp_smp2p_in: slave-kernel { qcom,entry-name = "slave-kernel"; interrupt-controller; #interrupt-cells = <2>; }; }; qcom,smp2p-modem { compatible = "qcom,smp2p"; qcom,smem = <435>, <428>; interrupt-parent = <&ipcc_mproc>; interrupts = <IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P IRQ_TYPE_EDGE_RISING>; mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P>; qcom,local-pid = <0>; qcom,remote-pid = <1>; modem_smp2p_out: master-kernel { qcom,entry-name = "master-kernel"; #qcom,smem-state-cells = <1>; }; modem_smp2p_in: slave-kernel { qcom,entry-name = "slave-kernel"; interrupt-controller; #interrupt-cells = <2>; }; smp2p_ipa_1_out: qcom,smp2p-ipa-1-out { qcom,entry-name = "ipa"; #qcom,smem-state-cells = <1>; }; /* ipa - inbound entry from mss */ smp2p_ipa_1_in: qcom,smp2p-ipa-1-in { qcom,entry-name = "ipa"; interrupt-controller; #interrupt-cells = <2>; }; }; qcom,smp2p-cdsp { compatible = "qcom,smp2p"; qcom,smem = <94>, <432>; interrupt-parent = <&ipcc_mproc>; interrupts = <IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P IRQ_TYPE_EDGE_RISING>; mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>; qcom,local-pid = <0>; qcom,remote-pid = <5>; cdsp_smp2p_out: master-kernel { qcom,entry-name = "master-kernel"; #qcom,smem-state-cells = <1>; }; cdsp_smp2p_in: slave-kernel { qcom,entry-name = "slave-kernel"; interrupt-controller; #interrupt-cells = <2>; }; }; rpm_msg_ram: memory@045f0000 { compatible = "qcom,rpm-msg-ram"; reg = <0x45f0000 0x7000>; }; rpm-glink { compatible = "qcom,glink-rpm"; qcom,rpm-msg-ram = <&rpm_msg_ram>; mboxes = <&ipcc_mproc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; mbox-names = "rpm_smem"; interrupt-parent = <&ipcc_mproc>; interrupts = <IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; qcom,rpm_glink_ssr { qcom,glink-channels = "glink_ssr"; qcom,notify-edges = <&glink_modem>, <&glink_adsp>, <&glink_cdsp>; }; }; qcom,glink { compatible = "qcom,glink"; #address-cells = <1>; #size-cells = <1>; ranges; glink_modem: modem { qcom,remote-pid = <1>; transport = "smem"; mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_GLINK_QMP>; mbox-names = "mpss_smem"; interrupt-parent = <&ipcc_mproc>; interrupts = <IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; label = "modem"; qcom,glink-label = "mpss"; qcom,modem_qrtr { qcom,glink-channels = "IPCRTR"; qcom,low-latency; qcom,intents = <0x800 5 0x2000 3 0x4400 2>; }; qcom,modem_ds { qcom,glink-channels = "DS"; qcom,intents = <0x4000 0x2>; }; qcom,modem_glink_ssr { qcom,glink-channels = "glink_ssr"; qcom,notify-edges = <&glink_adsp>; }; }; glink_adsp: adsp { qcom,remote-pid = <2>; transport = "smem"; mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_GLINK_QMP>; mbox-names = "adsp_smem"; interrupt-parent = <&ipcc_mproc>; interrupts = <IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; label = "adsp"; qcom,glink-label = "lpass"; qcom,adsp_qrtr { qcom,glink-channels = "IPCRTR"; qcom,intents = <0x800 5 0x2000 3 0x4400 2>; }; qcom,adsp_glink_ssr { qcom,glink-channels = "glink_ssr"; qcom,notify-edges = <&glink_modem>; }; qcom,pmic_glink_rpmsg { qcom,glink-channels = "PMIC_RTR_ADSP_APPS"; }; qcom,pmic_glink_log_rpmsg { qcom,glink-channels = "PMIC_LOGS_ADSP_APPS"; qcom,intents = <0x800 5 0xc00 3>; }; }; glink_cdsp: cdsp { qcom,remote-pid = <5>; transport = "smem"; mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_GLINK_QMP>; mbox-names = "dsps_smem"; interrupt-parent = <&ipcc_mproc>; interrupts = <IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; label = "cdsp"; qcom,glink-label = "cdsp"; qcom,cdsp_qrtr { qcom,glink-channels = "IPCRTR"; qcom,intents = <0x800 5 0x2000 3 0x4400 2>; }; }; }; qcom,glinkpkt { compatible = "qcom,glinkpkt"; qcom,glinkpkt-at-mdm0 { qcom,glinkpkt-edge = "mpss"; qcom,glinkpkt-ch-name = "DS"; qcom,glinkpkt-dev-name = "at_mdm0"; }; qcom,glinkpkt-apr-apps2 { qcom,glinkpkt-edge = "adsp"; qcom,glinkpkt-ch-name = "apr_apps2"; qcom,glinkpkt-dev-name = "apr_apps2"; }; qcom,glinkpkt-data40-cntl { qcom,glinkpkt-edge = "mpss"; qcom,glinkpkt-ch-name = "DATA40_CNTL"; qcom,glinkpkt-dev-name = "smdcntl8"; }; qcom,glinkpkt-data1 { qcom,glinkpkt-edge = "mpss"; qcom,glinkpkt-ch-name = "DATA1"; qcom,glinkpkt-dev-name = "smd7"; }; qcom,glinkpkt-data4 { qcom,glinkpkt-edge = "mpss"; qcom,glinkpkt-ch-name = "DATA4"; qcom,glinkpkt-dev-name = "smd8"; }; qcom,glinkpkt-data11 { qcom,glinkpkt-edge = "mpss"; qcom,glinkpkt-ch-name = "DATA11"; qcom,glinkpkt-dev-name = "smd11"; }; }; }; #include "holi-pinctrl.dtsi" Loading