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Commit 8929975e authored by Tony Truong's avatar Tony Truong
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ARM: dts: msm: add sleep state for PCIe0 CLKREQ for lahaina 

When PCIe0 core enters D3cold, switch CLKREQ# to function 0
to prevent leakage on lahaina.

Change-Id: I72d00cdf0331f1380821bfe14652eb09c1930d28
parent 1413240a

qcom/lahaina-pcie.dtsi

+4 −1
Original line number Diff line number Diff line
@@ -37,10 +37,13 @@ 


		perst-gpio = <&tlmm 94 0>;

		wake-gpio = <&tlmm 96 0>;

		pinctrl-names = "default";

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&pcie0_perst_default

				&pcie0_clkreq_default

				&pcie0_wake_default>;

		pinctrl-1 = <&pcie0_perst_default

				&pcie0_clkreq_sleep

				&pcie0_wake_default>;



		gdsc-vdd-supply = <&gcc_pcie_0_gdsc>;

		vreg-1p8-supply = <&pm8350_l6>;

qcom/lahaina-pinctrl.dtsi

+13 −0
Original line number Diff line number Diff line
@@ -2873,6 +2873,19 @@ 
				bias-pull-up;

			};

		};



		pcie0_clkreq_sleep: pcie0_clkreq_sleep {

			mux {

				pins = "gpio95";

				function = "gpio";

			};



			config {

				pins = "gpio95";

				drive-strength = <2>;

				bias-pull-up;

			};

		};

	};



	pcie1 {