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Commit 8873580d authored by Govindaraj Rajagopal's avatar Govindaraj Rajagopal Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: Remove core clock reset for shima 

Remove core clock reset to be inline with lahaina sequence.

Change-Id: If6e9bde30ec4f73535bf53303805c43cb9b6f693
parent 79f86ccf

qcom/shima-vidc.dtsi

+2 −3
Original line number Diff line number Diff line
@@ -26,9 +26,8 @@ 
		qcom,clock-configs = <0x0 0x0 0x1 0x1>;

		qcom,allowed-clock-rates = <240000000 338000000

			364800000>;

		resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,

			<&videocc VIDEO_CC_MVS0C_CLK_ARES>;

		reset-names = "video_axi_reset", "video_core_reset";

		resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>;

		reset-names = "video_axi_reset";



		qcom,reg-presets = <0xB0088 0x0 0x11>;