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Commit 887012e8 authored by Jeff Kirsher's avatar Jeff Kirsher
Browse files

ixgbe: enable relaxed ordering for SPARC 



This patch makes sure that relaxed ordering is not disabled when
on SPARC, where it helps with performance.

CC: <kernel-team@fb.com>
CC: Sowmini Varadhan <sowmini.varadhan@oracle.com>
Reported-by: default avatarSowmini Varadhan <sowmini.varadhan@oracle.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
Tested-by: default avatarPhil Schmitt <phillip.j.schmitt@intel.com>
parent bc035fc5

drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c

+6 −2
Original line number Diff line number Diff line
@@ -171,17 +171,21 @@ static s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw) 
 *  @hw: pointer to hardware structure

 *

 *  Starts the hardware using the generic start_hw function.

 *  Disables relaxed ordering Then set pcie completion timeout

 *  Disables relaxed ordering for archs other than SPARC

 *  Then set pcie completion timeout

 *

 **/

static s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw)

{

#ifndef CONFIG_SPARC

	u32 regval;

	u32 i;

#endif

	s32 ret_val;



	ret_val = ixgbe_start_hw_generic(hw);



#ifndef CONFIG_SPARC

	/* Disable relaxed ordering */

	for (i = 0; ((i < hw->mac.max_tx_queues) &&

	     (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
@@ -197,7 +201,7 @@ static s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw) 
			    IXGBE_DCA_RXCTRL_HEAD_WRO_EN);

		IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);

	}



#endif

	if (ret_val)

		return ret_val;

drivers/net/ethernet/intel/ixgbe/ixgbe_common.c

+6 −2
Original line number Diff line number Diff line
@@ -312,7 +312,6 @@ s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw) 
s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)

{

	u32 i;

	u32 regval;



	/* Clear the rate limiters */

	for (i = 0; i < hw->mac.max_tx_queues; i++) {
@@ -321,20 +320,25 @@ s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw) 
	}

	IXGBE_WRITE_FLUSH(hw);



#ifndef CONFIG_SPARC

	/* Disable relaxed ordering */

	for (i = 0; i < hw->mac.max_tx_queues; i++) {

		u32 regval;



		regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));

		regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;

		IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);

	}



	for (i = 0; i < hw->mac.max_rx_queues; i++) {

		u32 regval;



		regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));

		regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |

			    IXGBE_DCA_RXCTRL_HEAD_WRO_EN);

		IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);

	}



#endif

	return 0;

}