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Commit 884881ee authored by Taniya Das's avatar Taniya Das Committed by Saurabh Sahu
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clk: qcom: smd_rpm: RPM-SDM changes for XO BUFFERS in HOLI 



Add the support for PMIC G resource id for PMIC XO clocks
for HOLI.

Change-Id: I37f4179df1164a25c0974a0bcb7c8504c1491d5f
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent 0e2097ce

drivers/clk/qcom/clk-smd-rpm.c

+100 −54
Original line number Diff line number Diff line
@@ -122,14 +122,14 @@ 
		__DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id,   \

		0, QCOM_RPM_SMD_KEY_STATE)



#define DEFINE_CLK_SMD_RPM_XO_BUFFER(_platform, _name, _active, r_id)	      \

#define DEFINE_CLK_SMD_RPM_XO_BUFFER(_platform, _name, _active, type, r_id)   \

		__DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active,	      \

		QCOM_SMD_RPM_CLK_BUF_A, r_id, 0, 1000,			      \

		type, r_id, 0, 1000,			      \

		QCOM_RPM_KEY_SOFTWARE_ENABLE)



#define DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(_platform, _name, _active, r_id) \

		__DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active,	      \

		QCOM_SMD_RPM_CLK_BUF_A, r_id, 0, 1000,			      \

#define DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(_platform, _name, _active, type, \

		 r_id) __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, \

		type, r_id, 0, 1000,			      \

		QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY)



#define to_clk_smd_rpm(_hw) container_of(_hw, struct clk_smd_rpm, hw)
@@ -460,15 +460,22 @@ DEFINE_CLK_SMD_RPM(msm8916, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0); 
DEFINE_CLK_SMD_RPM(msm8916, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);

DEFINE_CLK_SMD_RPM(msm8916, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);

DEFINE_CLK_SMD_RPM_QDSS(msm8916, qdss_clk, qdss_a_clk, QCOM_SMD_RPM_MISC_CLK, 1);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, bb_clk1, bb_clk1_a, 1);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, bb_clk2, bb_clk2_a, 2);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, rf_clk1, rf_clk1_a, 4);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, rf_clk2, rf_clk2_a, 5);

DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, bb_clk1_pin, bb_clk1_a_pin, 1);

DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, bb_clk2_pin, bb_clk2_a_pin, 2);

DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk1_pin, rf_clk1_a_pin, 4);

DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk2_pin, rf_clk2_a_pin, 5);



DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, bb_clk1, bb_clk1_a,

						QCOM_SMD_RPM_CLK_BUF_A, 1);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, bb_clk2, bb_clk2_a,

						QCOM_SMD_RPM_CLK_BUF_A, 2);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, rf_clk1, rf_clk1_a,

						QCOM_SMD_RPM_CLK_BUF_A, 4);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, rf_clk2, rf_clk2_a,

						QCOM_SMD_RPM_CLK_BUF_A, 5);

DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, bb_clk1_pin, bb_clk1_a_pin,

						QCOM_SMD_RPM_CLK_BUF_A, 1);

DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, bb_clk2_pin, bb_clk2_a_pin,

						QCOM_SMD_RPM_CLK_BUF_A, 2);

DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk1_pin, rf_clk1_a_pin,

						QCOM_SMD_RPM_CLK_BUF_A, 4);

DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk2_pin, rf_clk2_a_pin,

						QCOM_SMD_RPM_CLK_BUF_A, 5);

static struct clk_hw *msm8916_clks[] = {

	[RPM_SMD_PCNOC_CLK]		= &msm8916_pcnoc_clk.hw,

	[RPM_SMD_PCNOC_A_CLK]		= &msm8916_pcnoc_a_clk.hw,
@@ -510,19 +517,32 @@ DEFINE_CLK_SMD_RPM(msm8974, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0); 
DEFINE_CLK_SMD_RPM(msm8974, gfx3d_clk_src, gfx3d_a_clk_src, QCOM_SMD_RPM_MEM_CLK, 1);

DEFINE_CLK_SMD_RPM(msm8974, ocmemgx_clk, ocmemgx_a_clk, QCOM_SMD_RPM_MEM_CLK, 2);

DEFINE_CLK_SMD_RPM_QDSS(msm8974, qdss_clk, qdss_a_clk, QCOM_SMD_RPM_MISC_CLK, 1);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_d0, cxo_d0_a, 1);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_d1, cxo_d1_a, 2);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_a0, cxo_a0_a, 4);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_a1, cxo_a1_a, 5);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_a2, cxo_a2_a, 6);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, diff_clk, diff_a_clk, 7);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, div_clk1, div_a_clk1, 11);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, div_clk2, div_a_clk2, 12);

DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_d0_pin, cxo_d0_a_pin, 1);

DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_d1_pin, cxo_d1_a_pin, 2);

DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a0_pin, cxo_a0_a_pin, 4);

DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a1_pin, cxo_a1_a_pin, 5);

DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a2_pin, cxo_a2_a_pin, 6);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_d0, cxo_d0_a,

				QCOM_SMD_RPM_CLK_BUF_A, 1);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_d1, cxo_d1_a,

				QCOM_SMD_RPM_CLK_BUF_A, 2);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_a0, cxo_a0_a,

				QCOM_SMD_RPM_CLK_BUF_A, 4);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_a1, cxo_a1_a,

				QCOM_SMD_RPM_CLK_BUF_A, 5);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_a2, cxo_a2_a,

				QCOM_SMD_RPM_CLK_BUF_A, 6);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, diff_clk, diff_a_clk,

				QCOM_SMD_RPM_CLK_BUF_A, 7);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, div_clk1, div_a_clk1,

				QCOM_SMD_RPM_CLK_BUF_A, 11);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, div_clk2, div_a_clk2,

				QCOM_SMD_RPM_CLK_BUF_A, 12);

DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_d0_pin, cxo_d0_a_pin,

				QCOM_SMD_RPM_CLK_BUF_A, 1);

DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_d1_pin, cxo_d1_a_pin,

				QCOM_SMD_RPM_CLK_BUF_A, 2);

DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a0_pin, cxo_a0_a_pin,

				QCOM_SMD_RPM_CLK_BUF_A, 4);

DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a1_pin, cxo_a1_a_pin,

				QCOM_SMD_RPM_CLK_BUF_A, 5);

DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a2_pin, cxo_a2_a_pin,

				QCOM_SMD_RPM_CLK_BUF_A, 6);



static struct clk_hw *msm8974_clks[] = {

	[RPM_SMD_PNOC_CLK]		= &msm8974_pnoc_clk.hw,
@@ -587,18 +607,30 @@ DEFINE_CLK_SMD_RPM_BRANCH(msm8996, aggre2_noc_clk, aggre2_noc_a_clk, 
			  QCOM_SMD_RPM_AGGR_CLK, 2, 1000);

DEFINE_CLK_SMD_RPM_QDSS(msm8996, qdss_clk, qdss_a_clk,

			QCOM_SMD_RPM_MISC_CLK, 1);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, bb_clk1, bb_clk1_a, 1);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, bb_clk2, bb_clk2_a, 2);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, rf_clk1, rf_clk1_a, 4);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, rf_clk2, rf_clk2_a, 5);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, ln_bb_clk, ln_bb_a_clk, 8);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, div_clk1, div_clk1_a, 0xb);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, div_clk2, div_clk2_a, 0xc);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, div_clk3, div_clk3_a, 0xd);

DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8996, bb_clk1_pin, bb_clk1_a_pin, 1);

DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8996, bb_clk2_pin, bb_clk2_a_pin, 2);

DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8996, rf_clk1_pin, rf_clk1_a_pin, 4);

DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8996, rf_clk2_pin, rf_clk2_a_pin, 5);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, bb_clk1, bb_clk1_a,

				QCOM_SMD_RPM_CLK_BUF_A, 1);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, bb_clk2, bb_clk2_a,

				QCOM_SMD_RPM_CLK_BUF_A, 2);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, rf_clk1, rf_clk1_a,

				QCOM_SMD_RPM_CLK_BUF_A, 4);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, rf_clk2, rf_clk2_a,

				QCOM_SMD_RPM_CLK_BUF_A, 5);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, ln_bb_clk, ln_bb_a_clk,

				QCOM_SMD_RPM_CLK_BUF_A, 8);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, div_clk1, div_clk1_a,

				QCOM_SMD_RPM_CLK_BUF_A, 0xb);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, div_clk2, div_clk2_a,

				QCOM_SMD_RPM_CLK_BUF_A, 0xc);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, div_clk3, div_clk3_a,

				QCOM_SMD_RPM_CLK_BUF_A, 0xd);

DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8996, bb_clk1_pin, bb_clk1_a_pin,

				QCOM_SMD_RPM_CLK_BUF_A, 1);

DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8996, bb_clk2_pin, bb_clk2_a_pin,

				QCOM_SMD_RPM_CLK_BUF_A, 2);

DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8996, rf_clk1_pin, rf_clk1_a_pin,

				QCOM_SMD_RPM_CLK_BUF_A, 4);

DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8996, rf_clk2_pin, rf_clk2_a_pin,

				QCOM_SMD_RPM_CLK_BUF_A, 5);



static struct clk_hw *msm8996_clks[] = {

	[RPM_SMD_PCNOC_CLK] = &msm8996_pcnoc_clk.hw,
@@ -664,11 +696,15 @@ DEFINE_CLK_SMD_RPM(qcs404, bimc_gpu_clk, bimc_gpu_a_clk, QCOM_SMD_RPM_MEM_CLK, 2 
DEFINE_CLK_SMD_RPM(qcs404, qpic_clk, qpic_a_clk, QCOM_SMD_RPM_QPIC_CLK, 0);

DEFINE_CLK_SMD_RPM(qcs404, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0);



DEFINE_CLK_SMD_RPM_XO_BUFFER(qcs404, rf_clk1, rf_clk1_a, 4);

DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(qcs404, rf_clk1_pin, rf_clk1_a_pin, 4);

DEFINE_CLK_SMD_RPM_XO_BUFFER(qcs404, rf_clk1, rf_clk1_a,

				QCOM_SMD_RPM_CLK_BUF_A, 4);

DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(qcs404, rf_clk1_pin, rf_clk1_a_pin,

				QCOM_SMD_RPM_CLK_BUF_A, 4);



DEFINE_CLK_SMD_RPM_XO_BUFFER(qcs404, ln_bb_clk, ln_bb_a_clk, 8);

DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(qcs404, ln_bb_clk_pin, ln_bb_clk_a_pin, 8);

DEFINE_CLK_SMD_RPM_XO_BUFFER(qcs404, ln_bb_clk, ln_bb_a_clk,

				QCOM_SMD_RPM_CLK_BUF_A, 8);

DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(qcs404, ln_bb_clk_pin, ln_bb_clk_a_pin,

				QCOM_SMD_RPM_CLK_BUF_A, 8);



static struct clk_hw *qcs404_clks[] = {

	[RPM_SMD_QDSS_CLK] = &qcs404_qdss_clk.hw,
@@ -702,12 +738,15 @@ DEFINE_CLK_SMD_RPM(msm8998, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0); 
DEFINE_CLK_SMD_RPM(msm8998, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);

DEFINE_CLK_SMD_RPM(msm8998, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);

DEFINE_CLK_SMD_RPM(msm8998, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, div_clk1, div_clk1_a, 0xb);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, div_clk1, div_clk1_a,

				QCOM_SMD_RPM_CLK_BUF_A, 0xb);

DEFINE_CLK_SMD_RPM(msm8998, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, ln_bb_clk1, ln_bb_clk1_a, 1);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, ln_bb_clk2, ln_bb_clk2_a, 2);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, ln_bb_clk1, ln_bb_clk1_a,

				QCOM_SMD_RPM_CLK_BUF_A, 1);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, ln_bb_clk2, ln_bb_clk2_a,

				QCOM_SMD_RPM_CLK_BUF_A, 2);

DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, ln_bb_clk3_pin, ln_bb_clk3_a_pin,

				     3);

					QCOM_SMD_RPM_CLK_BUF_A, 3);

DEFINE_CLK_SMD_RPM(msm8998, mmssnoc_axi_rpm_clk, mmssnoc_axi_rpm_a_clk,

		   QCOM_SMD_RPM_MMAXI_CLK, 0);

DEFINE_CLK_SMD_RPM(msm8998, aggre1_noc_clk, aggre1_noc_a_clk,
@@ -716,10 +755,14 @@ DEFINE_CLK_SMD_RPM(msm8998, aggre2_noc_clk, aggre2_noc_a_clk, 
		   QCOM_SMD_RPM_AGGR_CLK, 2);

DEFINE_CLK_SMD_RPM_QDSS(msm8998, qdss_clk, qdss_a_clk,

			QCOM_SMD_RPM_MISC_CLK, 1);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, rf_clk1, rf_clk1_a, 4);

DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, rf_clk2_pin, rf_clk2_a_pin, 5);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, rf_clk3, rf_clk3_a, 6);

DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, rf_clk3_pin, rf_clk3_a_pin, 6);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, rf_clk1, rf_clk1_a,

				QCOM_SMD_RPM_CLK_BUF_A, 4);

DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, rf_clk2_pin, rf_clk2_a_pin,

					QCOM_SMD_RPM_CLK_BUF_A, 5);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, rf_clk3, rf_clk3_a,

				QCOM_SMD_RPM_CLK_BUF_A, 6);

DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, rf_clk3_pin, rf_clk3_a_pin,

					QCOM_SMD_RPM_CLK_BUF_A, 6);



static struct clk_hw *msm8998_clks[] = {

	[RPM_SMD_BIMC_CLK] = &msm8998_bimc_clk.hw,
@@ -786,9 +829,12 @@ DEFINE_CLK_SMD_RPM(holi, hwkm_clk, hwkm_a_clk, QCOM_SMD_RPM_HWKM_CLK, 0); 
DEFINE_CLK_SMD_RPM(holi, pka_clk, pka_a_clk, QCOM_SMD_RPM_PKA_CLK, 0);



/* SMD_XO_BUFFER */

DEFINE_CLK_SMD_RPM_XO_BUFFER(holi, ln_bb_clk2, ln_bb_clk2_a, 8);

DEFINE_CLK_SMD_RPM_XO_BUFFER(holi, ln_bb_clk3, ln_bb_clk3_a, 9);

DEFINE_CLK_SMD_RPM_XO_BUFFER(holi, rf_clk5, rf_clk5_a, 6);

DEFINE_CLK_SMD_RPM_XO_BUFFER(holi, ln_bb_clk2, ln_bb_clk2_a,

				QCOM_SMD_RPM_CLK_BUF_G, 8);

DEFINE_CLK_SMD_RPM_XO_BUFFER(holi, ln_bb_clk3, ln_bb_clk3_a,

				QCOM_SMD_RPM_CLK_BUF_G, 9);

DEFINE_CLK_SMD_RPM_XO_BUFFER(holi, rf_clk5, rf_clk5_a,

				QCOM_SMD_RPM_CLK_BUF_G, 6);



/* Holi */

static struct clk_hw *holi_clks[] = {

include/linux/soc/qcom/smd-rpm.h

+1 −0
Original line number Diff line number Diff line
@@ -16,6 +16,7 @@ struct qcom_smd_rpm; 
#define QCOM_SMD_RPM_BUS_MASTER	0x73616d62

#define QCOM_SMD_RPM_BUS_SLAVE	0x766c7362

#define QCOM_SMD_RPM_CLK_BUF_A	0x616B6C63

#define QCOM_SMD_RPM_CLK_BUF_G	0x676B6C63

#define QCOM_SMD_RPM_LDOA	0x616f646c

#define QCOM_SMD_RPM_LDOB	0x626F646C

#define QCOM_SMD_RPM_MEM_CLK	0x326b6c63