Loading soc/swr-mstr-ctrl.c +4 −0 Original line number Diff line number Diff line Loading @@ -129,6 +129,7 @@ static void swrm_unlock_sleep(struct swr_mstr_ctrl *swrm); static u32 swr_master_read(struct swr_mstr_ctrl *swrm, unsigned int reg_addr); static void swr_master_write(struct swr_mstr_ctrl *swrm, u16 reg_addr, u32 val); static int swrm_runtime_resume(struct device *dev); static void swrm_wait_for_fifo_avail(struct swr_mstr_ctrl *swrm, int swrm_rd_wr); static u64 swrm_phy_dev[] = { 0, Loading Loading @@ -678,6 +679,9 @@ static int swr_master_bulk_write(struct swr_mstr_ctrl *swrm, u32 *reg_addr, * This still meets the hardware spec */ usleep_range(50, 55); if (reg_addr[i] == SWRM_CMD_FIFO_WR_CMD) swrm_wait_for_fifo_avail(swrm, SWRM_WR_CHECK_AVAIL); swr_master_write(swrm, reg_addr[i], val[i]); } usleep_range(100, 110); Loading Loading
soc/swr-mstr-ctrl.c +4 −0 Original line number Diff line number Diff line Loading @@ -129,6 +129,7 @@ static void swrm_unlock_sleep(struct swr_mstr_ctrl *swrm); static u32 swr_master_read(struct swr_mstr_ctrl *swrm, unsigned int reg_addr); static void swr_master_write(struct swr_mstr_ctrl *swrm, u16 reg_addr, u32 val); static int swrm_runtime_resume(struct device *dev); static void swrm_wait_for_fifo_avail(struct swr_mstr_ctrl *swrm, int swrm_rd_wr); static u64 swrm_phy_dev[] = { 0, Loading Loading @@ -678,6 +679,9 @@ static int swr_master_bulk_write(struct swr_mstr_ctrl *swrm, u32 *reg_addr, * This still meets the hardware spec */ usleep_range(50, 55); if (reg_addr[i] == SWRM_CMD_FIFO_WR_CMD) swrm_wait_for_fifo_avail(swrm, SWRM_WR_CHECK_AVAIL); swr_master_write(swrm, reg_addr[i], val[i]); } usleep_range(100, 110); Loading