Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 87c8a237 authored by Akshaya Bhat's avatar Akshaya Bhat
Browse files

ARM: dts: msm: Add initial device tree for SA2150P 

Add initial device tree for SA2150P target.

Change-Id: I107ed97c75f15c91e94a470182d4ec749abce7a8
parent 7dea9d66

bindings/arm/msm/msm.txt

+4 −0
Original line number Diff line number Diff line
@@ -163,6 +163,9 @@ Generic board variants: 
- HDK device:

  compatible = "qcom,hdk"



- SA2150P

  compatible = "qcom,sa2150p"





Boards (SoC type + board variant):
@@ -272,6 +275,7 @@ compatible = "qcom,sa6155-adp-air" 
compatible = "qcom,sa6155p-adp-air"

compatible = "qcom,qcs405-rumi"

compatible = "qcom,qcs405-iot"

compatible = "qcom,sa2150p-ccard"

compatible = "qcom,qcs403-iot"

compatible = "qcom,sa8150-adp-star"

compatible = "qcom,adp-star"

bindings/interrupt-controller/qcom,mpm.txt

+1 −0
Original line number Diff line number Diff line
@@ -27,6 +27,7 @@ Properties: 
		"qcom,mpm-gic-scuba"

		"qcom,mpm-gic-sdxnightjar"

		"qcom,mpm-gic-monaco"

		"qcom,mpm-gic-qcs405"



- interrupts:

	Usage: required

qcom/Makefile

+2 −0
Original line number Diff line number Diff line
@@ -357,6 +357,8 @@ else 
dtb-$(CONFIG_ARCH_SA8195)	+= sa8195p-adp-star.dtb \

	sa8195p-v2-adp-air.dtb

endif



dtb-$(CONFIG_ARCH_SA2150P) += sa2150p-ccard-emmc.dtb

endif



ifeq ($(CONFIG_ARCH_LAHAINA), y)

qcom/qcs405-cpu.dtsi

0 → 100644
+114 −0
Original line number Diff line number Diff line 
/ {

	psci {

		compatible = "arm,psci-1.0";

		method = "smc";

	};



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;

		cpu-map {

			cluster0 {

				core0 {

					cpu = <&CPU0>;

				};



				core1 {

					cpu = <&CPU1>;

				};



				core2 {

					cpu = <&CPU2>;

				};



				core3 {

					cpu = <&CPU3>;

				};

			};

		};



		CPU0: cpu@100 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x100>;

			enable-method = "psci";

			capacity-dmips-mhz = <1024>;

			next-level-cache = <&L2_1>;

			#cooling-cells = <2>;

			L2_1: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-level = <2>;

			      /* A53 L2 dump not supported */

			      qcom,dump-size = <0x0>;

			};



			L1_I_100: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x8800>;

			};



			L1_D_100: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9000>;

			};

		};



		CPU1: cpu@101 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x101>;

			enable-method = "psci";

			capacity-dmips-mhz = <1024>;

			next-level-cache = <&L2_1>;

			#cooling-cells = <2>;

			L1_I_101: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x8800>;

			};



			L1_D_101: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9000>;

			};

		};



		CPU2: cpu@102 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x102>;

			enable-method = "psci";

			capacity-dmips-mhz = <1024>;

			next-level-cache = <&L2_1>;

			#cooling-cells = <2>;

			L1_I_102: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x8800>;

			};



			L1_D_102: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9000>;

			};

		};



		CPU3: cpu@103 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x103>;

			enable-method = "psci";

			capacity-dmips-mhz = <1024>;

			next-level-cache = <&L2_1>;

			#cooling-cells = <2>;

			L1_I_103: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x8800>;

			};



			L1_D_103: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9000>;

			};

		};

	};



};

qcom/qcs405-pinctrl.dtsi

0 → 100644
+28 −0
Original line number Diff line number Diff line 
&soc {

	tlmm: pinctrl@1000000 {

		compatible = "qcom,qcs404-pinctrl";

		reg = <0x01000000 0x200000>,

		      <0x01300000 0x200000>,

		      <0x07b00000 0x200000>;

		reg-names = "south", "north", "east";

		interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-controller;

		#interrupt-cells = <2>;

		gpio-ranges = <&tlmm 0 0 120>;

		gpio-controller;

		#gpio-cells = <2>;



		blsp1_uart2_default: blsp1-uart2-default {

			rx {

				pins = "gpio18";

				function = "blsp_uart_rx_a2";

			};



			tx {

				pins = "gpio17";

				function = "blsp_uart_tx_a2";

			};

		};



	};

};