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Commit 87c2ee74 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-next-4.20' of git://people.freedesktop.org/~agd5f/linux into drm-next 



More new features and fixes for 4.20:
- Add dynamic powergating support for VCN on picasso
- Scheduler cleanup
- Vega20 support for KFD
- DC cleanups and bug fixes

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180927184348.2696-1-alexander.deucher@amd.com
parents 2de0b0a1 6a962430

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+17 −7
Original line number Diff line number Diff line
@@ -146,6 +146,7 @@ extern int amdgpu_cik_support; 
#define AMDGPU_DEFAULT_GTT_SIZE_MB		3072ULL /* 3GB by default */

#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS	        3000

#define AMDGPU_MAX_USEC_TIMEOUT			100000	/* 100 ms */

#define AMDGPU_FENCE_JIFFIES_TIMEOUT		(HZ / 2)

/* AMDGPU_IB_POOL_SIZE must be a power of 2 */

#define AMDGPU_IB_POOL_SIZE			16

#define AMDGPU_DEBUGFS_MAX_COMPONENTS		32
@@ -408,16 +409,25 @@ typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT 
	AMDGPU_DOORBELL64_GFX_RING0               = 0x8b,



	/*

	 * Other graphics doorbells can be allocated here: from 0x8c to 0xef

	 * Other graphics doorbells can be allocated here: from 0x8c to 0xdf

	 * Graphics voltage island aperture 1

	 * default non-graphics QWORD index is 0xF0 - 0xFF inclusive

	 * default non-graphics QWORD index is 0xe0 - 0xFF inclusive

	 */



	/* sDMA engines */

	AMDGPU_DOORBELL64_sDMA_ENGINE0            = 0xF0,

	AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0     = 0xF1,

	AMDGPU_DOORBELL64_sDMA_ENGINE1            = 0xF2,

	AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1     = 0xF3,

	/* sDMA engines  reserved from 0xe0 -oxef  */

	AMDGPU_DOORBELL64_sDMA_ENGINE0            = 0xE0,

	AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0     = 0xE1,

	AMDGPU_DOORBELL64_sDMA_ENGINE1            = 0xE8,

	AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1     = 0xE9,



	/* For vega10 sriov, the sdma doorbell must be fixed as follow

	 * to keep the same setting with host driver, or it will

	 * happen conflicts

	 */

	AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0            = 0xF0,

	AMDGPU_VEGA10_DOORBELL64_sDMA_HI_PRI_ENGINE0     = 0xF1,

	AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1            = 0xF2,

	AMDGPU_VEGA10_DOORBELL64_sDMA_HI_PRI_ENGINE1     = 0xF3,



	/* Interrupt handler */

	AMDGPU_DOORBELL64_IH                      = 0xF4,  /* For legacy interrupt ring buffer */

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c

+35 −15
Original line number Diff line number Diff line
@@ -76,6 +76,7 @@ void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev) 
		kfd2kgd = amdgpu_amdkfd_gfx_8_0_get_functions();

		break;

	case CHIP_VEGA10:

	case CHIP_VEGA20:

	case CHIP_RAVEN:

		kfd2kgd = amdgpu_amdkfd_gfx_9_0_get_functions();

		break;
@@ -123,7 +124,7 @@ static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, 


void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)

{

	int i;

	int i, n;

	int last_valid_bit;

	if (adev->kfd) {

		struct kgd2kfd_shared_resources gpu_resources = {
@@ -162,7 +163,15 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev) 
				&gpu_resources.doorbell_physical_address,

				&gpu_resources.doorbell_aperture_size,

				&gpu_resources.doorbell_start_offset);

		if (adev->asic_type >= CHIP_VEGA10) {



		if (adev->asic_type < CHIP_VEGA10) {

			kgd2kfd->device_init(adev->kfd, &gpu_resources);

			return;

		}



		n = (adev->asic_type < CHIP_VEGA20) ? 2 : 8;



		for (i = 0; i < n; i += 2) {

			/* On SOC15 the BIF is involved in routing

			 * doorbells using the low 12 bits of the

			 * address. Communicate the assignments to
@@ -170,20 +179,31 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev) 
			 * process in case of 64-bit doorbells so we

			 * can use each doorbell assignment twice.

			 */

			gpu_resources.sdma_doorbell[0][0] =

				AMDGPU_DOORBELL64_sDMA_ENGINE0;

			gpu_resources.sdma_doorbell[0][1] =

				AMDGPU_DOORBELL64_sDMA_ENGINE0 + 0x200;

			gpu_resources.sdma_doorbell[1][0] =

				AMDGPU_DOORBELL64_sDMA_ENGINE1;

			gpu_resources.sdma_doorbell[1][1] =

				AMDGPU_DOORBELL64_sDMA_ENGINE1 + 0x200;

			/* Doorbells 0x0f0-0ff and 0x2f0-2ff are reserved for

			if (adev->asic_type == CHIP_VEGA10) {

				gpu_resources.sdma_doorbell[0][i] =

					AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 + (i >> 1);

				gpu_resources.sdma_doorbell[0][i+1] =

					AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 + 0x200 + (i >> 1);

				gpu_resources.sdma_doorbell[1][i] =

					AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1 + (i >> 1);

				gpu_resources.sdma_doorbell[1][i+1] =

					AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1 + 0x200 + (i >> 1);

			} else {

				gpu_resources.sdma_doorbell[0][i] =

					AMDGPU_DOORBELL64_sDMA_ENGINE0 + (i >> 1);

				gpu_resources.sdma_doorbell[0][i+1] =

					AMDGPU_DOORBELL64_sDMA_ENGINE0 + 0x200 + (i >> 1);

				gpu_resources.sdma_doorbell[1][i] =

					AMDGPU_DOORBELL64_sDMA_ENGINE1 + (i >> 1);

				gpu_resources.sdma_doorbell[1][i+1] =

					AMDGPU_DOORBELL64_sDMA_ENGINE1 + 0x200 + (i >> 1);

			}

		}

		/* Doorbells 0x0e0-0ff and 0x2e0-2ff are reserved for

		 * SDMA, IH and VCN. So don't use them for the CP.

		 */

			gpu_resources.reserved_doorbell_mask = 0x1f0;

			gpu_resources.reserved_doorbell_val  = 0x0f0;

		}

		gpu_resources.reserved_doorbell_mask = 0x1e0;

		gpu_resources.reserved_doorbell_val  = 0x0e0;



		kgd2kfd->device_init(adev->kfd, &gpu_resources);

	}

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h

+1 −1
Original line number Diff line number Diff line
@@ -174,7 +174,7 @@ void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev, 
				struct amdgpu_vm *vm);

void amdgpu_amdkfd_gpuvm_destroy_process_vm(struct kgd_dev *kgd, void *vm);

void amdgpu_amdkfd_gpuvm_release_process_vm(struct kgd_dev *kgd, void *vm);

uint32_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *vm);

uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *vm);

int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(

		struct kgd_dev *kgd, uint64_t va, uint64_t size,

		void *vm, struct kgd_mem **mem,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

+4 −3
Original line number Diff line number Diff line
@@ -142,7 +142,7 @@ static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type); 
static void set_scratch_backing_va(struct kgd_dev *kgd,

					uint64_t va, uint32_t vmid);

static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,

		uint32_t page_table_base);

		uint64_t page_table_base);

static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid);

static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid);

static uint32_t read_vmid_from_vmfault_reg(struct kgd_dev *kgd);
@@ -874,7 +874,7 @@ static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type) 
}



static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,

			uint32_t page_table_base)

			uint64_t page_table_base)

{

	struct amdgpu_device *adev = get_amdgpu_device(kgd);
@@ -882,7 +882,8 @@ static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid, 
		pr_err("trying to set page table base for wrong VMID\n");

		return;

	}

	WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8, page_table_base);

	WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8,

		lower_32_bits(page_table_base));

}



static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid)

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

+6 −6
Original line number Diff line number Diff line
@@ -45,8 +45,6 @@ enum hqd_dequeue_request_type { 
	RESET_WAVES

};



struct vi_sdma_mqd;



/*

 * Register access functions

 */
@@ -100,7 +98,7 @@ static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type); 
static void set_scratch_backing_va(struct kgd_dev *kgd,

					uint64_t va, uint32_t vmid);

static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,

		uint32_t page_table_base);

		uint64_t page_table_base);

static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid);

static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid);
@@ -282,7 +280,8 @@ static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id) 


	lock_srbm(kgd, mec, pipe, 0, 0);



	WREG32(mmCPC_INT_CNTL, CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK);

	WREG32(mmCPC_INT_CNTL, CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK |

			CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK);



	unlock_srbm(kgd);
@@ -834,7 +833,7 @@ static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type) 
}



static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,

		uint32_t page_table_base)

		uint64_t page_table_base)

{

	struct amdgpu_device *adev = get_amdgpu_device(kgd);
@@ -842,7 +841,8 @@ static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid, 
		pr_err("trying to set page table base for wrong VMID\n");

		return;

	}

	WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8, page_table_base);

	WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8,

			lower_32_bits(page_table_base));

}



static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid)