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Commit 87aee0bf authored by Jack Pham's avatar Jack Pham
Browse files

usb: phy: qmp: Perform DP_COM_SW_RESET during portselect 



In case lane selection is not passed from controller, we can
default to using the HW based portselect signal. But in order
to ensure the signal is correctly latched from the PMIC, the
PHY must be reset using the USB3_DP_COM_SW_RESET register
prior to performing initialization. During this time ensure
that the default pinctrl configuration is selected which
places the pinmux in portselect mode.

Change-Id: I0b9ba53a538fad9f731fd1ca0a9d01751d57a063
Signed-off-by: default avatarJack Pham <jackp@codeaurora.org>
parent 7855a48f

drivers/usb/phy/phy-msm-ssusb-qmp.c

+14 −6
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2013-2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2013-2020, The Linux Foundation. All rights reserved.

 */



#include <linux/module.h>
@@ -17,6 +17,8 @@ 
#include <linux/clk.h>

#include <linux/extcon.h>

#include <linux/reset.h>

#include <linux/pinctrl/devinfo.h>

#include <linux/pinctrl/consumer.h>



enum core_ldo_levels {

	CORE_LEVEL_NONE = 0,
@@ -380,6 +382,17 @@ static void usb_qmp_update_portselect_phymode(struct msm_ssphy_qmp *phy) 


	switch (phy->phy_type) {

	case USB3_AND_DP:

		if (phy->phy.dev->pins) {

			writel_relaxed(0x01,

				phy->base + phy->phy_reg[USB3_DP_COM_SW_RESET]);



			pinctrl_select_state(phy->phy.dev->pins->p,

					phy->phy.dev->pins->default_state);



			writel_relaxed(0x00,

				phy->base + phy->phy_reg[USB3_DP_COM_SW_RESET]);

		}



		/* override hardware control for reset of qmp phy */

		writel_relaxed(SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |

			SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET,
@@ -489,11 +502,6 @@ static int msm_ssphy_qmp_init(struct usb_phy *uphy) 
		return ret;

	}



	/* perform software reset of PHY common logic */

	if (phy->phy_type == USB3_AND_DP)

		writel_relaxed(0x00,

			phy->base + phy->phy_reg[USB3_DP_COM_SW_RESET]);



	/* perform software reset of PCS/Serdes */

	writel_relaxed(0x00, phy->base + phy->phy_reg[USB3_PHY_SW_RESET]);

	/* start PCS/Serdes to operation mode */