dt-bindings: phy: meson-g12a-usb3-pcie-phy: convert to yaml

# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

# Copyright 2019 BayLibre, SAS

%YAML 1.2

---

$id: "http://devicetree.org/schemas/phy/amlogic,meson-g12a-usb3-pcie-phy.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Amlogic G12A USB3 + PCIE Combo PHY

maintainers:

  - Neil Armstrong <narmstrong@baylibre.com>

properties:

  compatible:

    enum:

      - amlogic,meson-g12a-usb3-pcie-phy

  reg:

    maxItems: 1

  clocks:

    maxItems: 1

  clock-names:

    items:

      - const: ref_clk

  resets:

    maxItems: 1

  reset-names:

    items:

      - const: phy

  "#phy-cells":

    const: 1

required:

  - compatible

  - reg

  - clocks

  - clock-names

  - resets

  - reset-names

  - "#phy-cells"

examples:

  - |

    phy@46000 {

          compatible = "amlogic,meson-g12a-usb3-pcie-phy";

          reg = <0x46000 0x2000>;

          clocks = <&ref_clk>;

          clock-names = "ref_clk";

          resets = <&phy_reset>;

          reset-names = "phy";

          #phy-cells = <1>;

    };

* Amlogic G12A USB3 + PCIE Combo PHY binding

Required properties:

- compatible:	Should be "amlogic,meson-g12a-usb3-pcie-phy"

- #phys-cells:	must be 1. The cell number is used to select the phy mode

  as defined in <dt-bindings/phy/phy.h> between PHY_TYPE_USB3 and PHY_TYPE_PCIE

- reg:		The base address and length of the registers

- clocks:	a phandle to the 100MHz reference clock of this PHY

- clock-names:	must be "ref_clk"

- resets:	phandle to the reset lines for the PHY control

- reset-names:	must be "phy"

Example:

	usb3_pcie_phy: phy@46000 {

		compatible = "amlogic,g12a-usb3-pcie-phy";

		reg = <0x0 0x46000 0x0 0x2000>;

		clocks = <&clkc CLKID_PCIE_PLL>;

		clock-names = "ref_clk";

		resets = <&reset RESET_PCIE_PHY>;

		reset-names = "phy";

		#phy-cells = <1>;

	};