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Commit 87173557 authored by Jerome Brunet's avatar Jerome Brunet
Browse files

clk: meson: clk-pll: remove od parameters 



Remove od parameters from pll clocks and add post dividers clocks
instead. Some clock, especially the one which feature several ods,
may provide output between those ods. Also, some drivers, such
as the hdmi driver, may require a more detailed control of the
clock dividers, compared to what CCF would perform automatically.

One added benefit of removing ods is that it also greatly reduce the
size of the rate parameter tables.

In the future, we could possibly take the predivider 'n' out of this
driver as well. To do so, we will need to understand the constraints
for the PLL to lock and whether or not it depends on the input clock
rate.

Acked-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
Reviewed-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: default avatarJerome Brunet <jbrunet@baylibre.com>
parent 2303a9ca

drivers/clk/meson/axg.c

+154 −130
Original line number Diff line number Diff line
@@ -22,7 +22,7 @@ 


static DEFINE_SPINLOCK(meson_clk_lock);



static struct clk_regmap axg_fixed_pll = {

static struct clk_regmap axg_fixed_pll_dco = {

	.data = &(struct meson_clk_pll_data){

		.en = {

			.reg_off = HHI_MPLL_CNTL,
@@ -39,11 +39,6 @@ static struct clk_regmap axg_fixed_pll = { 
			.shift   = 9,

			.width   = 5,

		},

		.od = {

			.reg_off = HHI_MPLL_CNTL,

			.shift   = 16,

			.width   = 2,

		},

		.frac = {

			.reg_off = HHI_MPLL_CNTL2,

			.shift   = 0,
@@ -61,14 +56,33 @@ static struct clk_regmap axg_fixed_pll = { 
		},

	},

	.hw.init = &(struct clk_init_data){

		.name = "fixed_pll",

		.name = "fixed_pll_dco",

		.ops = &meson_clk_pll_ro_ops,

		.parent_names = (const char *[]){ "xtal" },

		.num_parents = 1,

	},

};



static struct clk_regmap axg_sys_pll = {

static struct clk_regmap axg_fixed_pll = {

	.data = &(struct clk_regmap_div_data){

		.offset = HHI_MPLL_CNTL,

		.shift = 16,

		.width = 2,

		.flags = CLK_DIVIDER_POWER_OF_TWO,

	},

	.hw.init = &(struct clk_init_data){

		.name = "fixed_pll",

		.ops = &clk_regmap_divider_ro_ops,

		.parent_names = (const char *[]){ "fixed_pll_dco" },

		.num_parents = 1,

		/*

		 * This clock won't ever change at runtime so

		 * CLK_SET_RATE_PARENT is not required

		 */

	},

};



static struct clk_regmap axg_sys_pll_dco = {

	.data = &(struct meson_clk_pll_data){

		.en = {

			.reg_off = HHI_SYS_PLL_CNTL,
@@ -85,11 +99,6 @@ static struct clk_regmap axg_sys_pll = { 
			.shift   = 9,

			.width   = 5,

		},

		.od = {

			.reg_off = HHI_SYS_PLL_CNTL,

			.shift   = 16,

			.width   = 2,

		},

		.l = {

			.reg_off = HHI_SYS_PLL_CNTL,

			.shift   = 31,
@@ -102,101 +111,59 @@ static struct clk_regmap axg_sys_pll = { 
		},

	},

	.hw.init = &(struct clk_init_data){

		.name = "sys_pll",

		.name = "sys_pll_dco",

		.ops = &meson_clk_pll_ro_ops,

		.parent_names = (const char *[]){ "xtal" },

		.num_parents = 1,

	},

};



static struct clk_regmap axg_sys_pll = {

	.data = &(struct clk_regmap_div_data){

		.offset = HHI_SYS_PLL_CNTL,

		.shift = 16,

		.width = 2,

		.flags = CLK_DIVIDER_POWER_OF_TWO,

	},

	.hw.init = &(struct clk_init_data){

		.name = "sys_pll",

		.ops = &clk_regmap_divider_ro_ops,

		.parent_names = (const char *[]){ "sys_pll_dco" },

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,

	},

};



static const struct pll_rate_table axg_gp0_pll_rate_table[] = {

	PLL_RATE(240000000, 40, 1, 2),

	PLL_RATE(246000000, 41, 1, 2),

	PLL_RATE(252000000, 42, 1, 2),

	PLL_RATE(258000000, 43, 1, 2),

	PLL_RATE(264000000, 44, 1, 2),

	PLL_RATE(270000000, 45, 1, 2),

	PLL_RATE(276000000, 46, 1, 2),

	PLL_RATE(282000000, 47, 1, 2),

	PLL_RATE(288000000, 48, 1, 2),

	PLL_RATE(294000000, 49, 1, 2),

	PLL_RATE(300000000, 50, 1, 2),

	PLL_RATE(306000000, 51, 1, 2),

	PLL_RATE(312000000, 52, 1, 2),

	PLL_RATE(318000000, 53, 1, 2),

	PLL_RATE(324000000, 54, 1, 2),

	PLL_RATE(330000000, 55, 1, 2),

	PLL_RATE(336000000, 56, 1, 2),

	PLL_RATE(342000000, 57, 1, 2),

	PLL_RATE(348000000, 58, 1, 2),

	PLL_RATE(354000000, 59, 1, 2),

	PLL_RATE(360000000, 60, 1, 2),

	PLL_RATE(366000000, 61, 1, 2),

	PLL_RATE(372000000, 62, 1, 2),

	PLL_RATE(378000000, 63, 1, 2),

	PLL_RATE(384000000, 64, 1, 2),

	PLL_RATE(390000000, 65, 1, 3),

	PLL_RATE(396000000, 66, 1, 3),

	PLL_RATE(402000000, 67, 1, 3),

	PLL_RATE(408000000, 68, 1, 3),

	PLL_RATE(480000000, 40, 1, 1),

	PLL_RATE(492000000, 41, 1, 1),

	PLL_RATE(504000000, 42, 1, 1),

	PLL_RATE(516000000, 43, 1, 1),

	PLL_RATE(528000000, 44, 1, 1),

	PLL_RATE(540000000, 45, 1, 1),

	PLL_RATE(552000000, 46, 1, 1),

	PLL_RATE(564000000, 47, 1, 1),

	PLL_RATE(576000000, 48, 1, 1),

	PLL_RATE(588000000, 49, 1, 1),

	PLL_RATE(600000000, 50, 1, 1),

	PLL_RATE(612000000, 51, 1, 1),

	PLL_RATE(624000000, 52, 1, 1),

	PLL_RATE(636000000, 53, 1, 1),

	PLL_RATE(648000000, 54, 1, 1),

	PLL_RATE(660000000, 55, 1, 1),

	PLL_RATE(672000000, 56, 1, 1),

	PLL_RATE(684000000, 57, 1, 1),

	PLL_RATE(696000000, 58, 1, 1),

	PLL_RATE(708000000, 59, 1, 1),

	PLL_RATE(720000000, 60, 1, 1),

	PLL_RATE(732000000, 61, 1, 1),

	PLL_RATE(744000000, 62, 1, 1),

	PLL_RATE(756000000, 63, 1, 1),

	PLL_RATE(768000000, 64, 1, 1),

	PLL_RATE(780000000, 65, 1, 1),

	PLL_RATE(792000000, 66, 1, 1),

	PLL_RATE(804000000, 67, 1, 1),

	PLL_RATE(816000000, 68, 1, 1),

	PLL_RATE(960000000, 40, 1, 0),

	PLL_RATE(984000000, 41, 1, 0),

	PLL_RATE(1008000000, 42, 1, 0),

	PLL_RATE(1032000000, 43, 1, 0),

	PLL_RATE(1056000000, 44, 1, 0),

	PLL_RATE(1080000000, 45, 1, 0),

	PLL_RATE(1104000000, 46, 1, 0),

	PLL_RATE(1128000000, 47, 1, 0),

	PLL_RATE(1152000000, 48, 1, 0),

	PLL_RATE(1176000000, 49, 1, 0),

	PLL_RATE(1200000000, 50, 1, 0),

	PLL_RATE(1224000000, 51, 1, 0),

	PLL_RATE(1248000000, 52, 1, 0),

	PLL_RATE(1272000000, 53, 1, 0),

	PLL_RATE(1296000000, 54, 1, 0),

	PLL_RATE(1320000000, 55, 1, 0),

	PLL_RATE(1344000000, 56, 1, 0),

	PLL_RATE(1368000000, 57, 1, 0),

	PLL_RATE(1392000000, 58, 1, 0),

	PLL_RATE(1416000000, 59, 1, 0),

	PLL_RATE(1440000000, 60, 1, 0),

	PLL_RATE(1464000000, 61, 1, 0),

	PLL_RATE(1488000000, 62, 1, 0),

	PLL_RATE(1512000000, 63, 1, 0),

	PLL_RATE(1536000000, 64, 1, 0),

	PLL_RATE(1560000000, 65, 1, 0),

	PLL_RATE(1584000000, 66, 1, 0),

	PLL_RATE(1608000000, 67, 1, 0),

	PLL_RATE(1632000000, 68, 1, 0),

	PLL_RATE(960000000, 40, 1),

	PLL_RATE(984000000, 41, 1),

	PLL_RATE(1008000000, 42, 1),

	PLL_RATE(1032000000, 43, 1),

	PLL_RATE(1056000000, 44, 1),

	PLL_RATE(1080000000, 45, 1),

	PLL_RATE(1104000000, 46, 1),

	PLL_RATE(1128000000, 47, 1),

	PLL_RATE(1152000000, 48, 1),

	PLL_RATE(1176000000, 49, 1),

	PLL_RATE(1200000000, 50, 1),

	PLL_RATE(1224000000, 51, 1),

	PLL_RATE(1248000000, 52, 1),

	PLL_RATE(1272000000, 53, 1),

	PLL_RATE(1296000000, 54, 1),

	PLL_RATE(1320000000, 55, 1),

	PLL_RATE(1344000000, 56, 1),

	PLL_RATE(1368000000, 57, 1),

	PLL_RATE(1392000000, 58, 1),

	PLL_RATE(1416000000, 59, 1),

	PLL_RATE(1440000000, 60, 1),

	PLL_RATE(1464000000, 61, 1),

	PLL_RATE(1488000000, 62, 1),

	PLL_RATE(1512000000, 63, 1),

	PLL_RATE(1536000000, 64, 1),

	PLL_RATE(1560000000, 65, 1),

	PLL_RATE(1584000000, 66, 1),

	PLL_RATE(1608000000, 67, 1),

	PLL_RATE(1632000000, 68, 1),

	{ /* sentinel */ },

};
@@ -208,7 +175,7 @@ static const struct reg_sequence axg_gp0_init_regs[] = { 
	{ .reg = HHI_GP0_PLL_CNTL5,	.def = 0x00078000 },

};



static struct clk_regmap axg_gp0_pll = {

static struct clk_regmap axg_gp0_pll_dco = {

	.data = &(struct meson_clk_pll_data){

		.en = {

			.reg_off = HHI_GP0_PLL_CNTL,
@@ -225,11 +192,6 @@ static struct clk_regmap axg_gp0_pll = { 
			.shift   = 9,

			.width   = 5,

		},

		.od = {

			.reg_off = HHI_GP0_PLL_CNTL,

			.shift   = 16,

			.width   = 2,

		},

		.frac = {

			.reg_off = HHI_GP0_PLL_CNTL1,

			.shift   = 0,
@@ -250,13 +212,29 @@ static struct clk_regmap axg_gp0_pll = { 
		.init_count = ARRAY_SIZE(axg_gp0_init_regs),

	},

	.hw.init = &(struct clk_init_data){

		.name = "gp0_pll",

		.name = "gp0_pll_dco",

		.ops = &meson_clk_pll_ops,

		.parent_names = (const char *[]){ "xtal" },

		.num_parents = 1,

	},

};



static struct clk_regmap axg_gp0_pll = {

	.data = &(struct clk_regmap_div_data){

		.offset = HHI_GP0_PLL_CNTL,

		.shift = 16,

		.width = 2,

		.flags = CLK_DIVIDER_POWER_OF_TWO,

	},

	.hw.init = &(struct clk_init_data){

		.name = "gp0_pll",

		.ops = &clk_regmap_divider_ops,

		.parent_names = (const char *[]){ "gp0_pll_dco" },

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,

	},

};



static const struct reg_sequence axg_hifi_init_regs[] = {

	{ .reg = HHI_HIFI_PLL_CNTL1,	.def = 0xc084b000 },

	{ .reg = HHI_HIFI_PLL_CNTL2,	.def = 0xb75020be },
@@ -265,7 +243,7 @@ static const struct reg_sequence axg_hifi_init_regs[] = { 
	{ .reg = HHI_HIFI_PLL_CNTL5,	.def = 0x00058000 },

};



static struct clk_regmap axg_hifi_pll = {

static struct clk_regmap axg_hifi_pll_dco = {

	.data = &(struct meson_clk_pll_data){

		.en = {

			.reg_off = HHI_HIFI_PLL_CNTL,
@@ -282,11 +260,6 @@ static struct clk_regmap axg_hifi_pll = { 
			.shift   = 9,

			.width   = 5,

		},

		.od = {

			.reg_off = HHI_HIFI_PLL_CNTL,

			.shift   = 16,

			.width   = 2,

		},

		.frac = {

			.reg_off = HHI_HIFI_PLL_CNTL5,

			.shift   = 0,
@@ -308,13 +281,29 @@ static struct clk_regmap axg_hifi_pll = { 
		.flags = CLK_MESON_PLL_ROUND_CLOSEST,

	},

	.hw.init = &(struct clk_init_data){

		.name = "hifi_pll",

		.name = "hifi_pll_dco",

		.ops = &meson_clk_pll_ops,

		.parent_names = (const char *[]){ "xtal" },

		.num_parents = 1,

	},

};



static struct clk_regmap axg_hifi_pll = {

	.data = &(struct clk_regmap_div_data){

		.offset = HHI_HIFI_PLL_CNTL,

		.shift = 16,

		.width = 2,

		.flags = CLK_DIVIDER_POWER_OF_TWO,

	},

	.hw.init = &(struct clk_init_data){

		.name = "hifi_pll",

		.ops = &clk_regmap_divider_ops,

		.parent_names = (const char *[]){ "hifi_pll_dco" },

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,

	},

};



static struct clk_fixed_factor axg_fclk_div2_div = {

	.mult = 1,

	.div = 2,
@@ -644,11 +633,9 @@ static struct clk_regmap axg_mpll3 = { 


static const struct pll_rate_table axg_pcie_pll_rate_table[] = {

	{

		.rate	= 100000000,

		.rate	= 1600000000,

		.m	= 200,

		.n	= 3,

		.od	= 1,

		.od2	= 3,

	},

	{ /* sentinel */ },

};
@@ -660,9 +647,10 @@ static const struct reg_sequence axg_pcie_init_regs[] = { 
	{ .reg = HHI_PCIE_PLL_CNTL4,	.def = 0xc000004d },

	{ .reg = HHI_PCIE_PLL_CNTL5,	.def = 0x00078000 },

	{ .reg = HHI_PCIE_PLL_CNTL6,	.def = 0x002323c6 },

	{ .reg = HHI_PCIE_PLL_CNTL,     .def = 0x400106c8 },

};



static struct clk_regmap axg_pcie_pll = {

static struct clk_regmap axg_pcie_pll_dco = {

	.data = &(struct meson_clk_pll_data){

		.en = {

			.reg_off = HHI_PCIE_PLL_CNTL,
@@ -679,16 +667,6 @@ static struct clk_regmap axg_pcie_pll = { 
			.shift   = 9,

			.width   = 5,

		},

		.od = {

			.reg_off = HHI_PCIE_PLL_CNTL,

			.shift   = 16,

			.width   = 2,

		},

		.od2 = {

			.reg_off = HHI_PCIE_PLL_CNTL6,

			.shift   = 6,

			.width   = 2,

		},

		.frac = {

			.reg_off = HHI_PCIE_PLL_CNTL1,

			.shift   = 0,
@@ -709,13 +687,45 @@ static struct clk_regmap axg_pcie_pll = { 
		.init_count = ARRAY_SIZE(axg_pcie_init_regs),

	},

	.hw.init = &(struct clk_init_data){

		.name = "pcie_pll",

		.name = "pcie_pll_dco",

		.ops = &meson_clk_pll_ops,

		.parent_names = (const char *[]){ "xtal" },

		.num_parents = 1,

	},

};



static struct clk_regmap axg_pcie_pll_od = {

	.data = &(struct clk_regmap_div_data){

		.offset = HHI_PCIE_PLL_CNTL,

		.shift = 16,

		.width = 2,

		.flags = CLK_DIVIDER_POWER_OF_TWO,

	},

	.hw.init = &(struct clk_init_data){

		.name = "pcie_pll_od",

		.ops = &clk_regmap_divider_ops,

		.parent_names = (const char *[]){ "pcie_pll_dco" },

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,

	},

};



static struct clk_regmap axg_pcie_pll = {

	.data = &(struct clk_regmap_div_data){

		.offset = HHI_PCIE_PLL_CNTL6,

		.shift = 6,

		.width = 2,

		.flags = CLK_DIVIDER_POWER_OF_TWO,

	},

	.hw.init = &(struct clk_init_data){

		.name = "pcie_pll",

		.ops = &clk_regmap_divider_ops,

		.parent_names = (const char *[]){ "pcie_pll_od" },

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,

	},

};



static struct clk_regmap axg_pcie_mux = {

	.data = &(struct clk_regmap_mux_data){

		.offset = HHI_PCIE_PLL_CNTL6,
@@ -1128,6 +1138,12 @@ static struct clk_hw_onecell_data axg_hw_onecell_data = { 
		[CLKID_GEN_CLK_SEL]		= &axg_gen_clk_sel.hw,

		[CLKID_GEN_CLK_DIV]		= &axg_gen_clk_div.hw,

		[CLKID_GEN_CLK]			= &axg_gen_clk.hw,

		[CLKID_SYS_PLL_DCO]		= &axg_sys_pll_dco.hw,

		[CLKID_FIXED_PLL_DCO]		= &axg_fixed_pll_dco.hw,

		[CLKID_GP0_PLL_DCO]		= &axg_gp0_pll_dco.hw,

		[CLKID_HIFI_PLL_DCO]		= &axg_hifi_pll_dco.hw,

		[CLKID_PCIE_PLL_DCO]		= &axg_pcie_pll_dco.hw,

		[CLKID_PCIE_PLL_OD]		= &axg_pcie_pll_od.hw,

		[NR_CLKS]			= NULL,

	},

	.num = NR_CLKS,
@@ -1206,6 +1222,8 @@ static struct clk_regmap *const axg_clk_regmaps[] = { 
	&axg_fclk_div4,

	&axg_fclk_div5,

	&axg_fclk_div7,

	&axg_pcie_pll_dco,

	&axg_pcie_pll_od,

	&axg_pcie_pll,

	&axg_pcie_mux,

	&axg_pcie_ref,
@@ -1215,6 +1233,12 @@ static struct clk_regmap *const axg_clk_regmaps[] = { 
	&axg_gen_clk_sel,

	&axg_gen_clk_div,

	&axg_gen_clk,

	&axg_fixed_pll_dco,

	&axg_sys_pll_dco,

	&axg_gp0_pll_dco,

	&axg_hifi_pll_dco,

	&axg_pcie_pll_dco,

	&axg_pcie_pll_od,

};



static const struct of_device_id clkc_match_table[] = {

drivers/clk/meson/axg.h

+7 −1
Original line number Diff line number Diff line
@@ -133,8 +133,14 @@ 
#define CLKID_PCIE_REF				78

#define CLKID_GEN_CLK_SEL			82

#define CLKID_GEN_CLK_DIV			83

#define CLKID_SYS_PLL_DCO			85

#define CLKID_FIXED_PLL_DCO			86

#define CLKID_GP0_PLL_DCO			87

#define CLKID_HIFI_PLL_DCO			88

#define CLKID_PCIE_PLL_DCO			89

#define CLKID_PCIE_PLL_OD			90



#define NR_CLKS					85

#define NR_CLKS					91



/* include the CLKIDs that have been made part of the DT binding */

#include <dt-bindings/clock/axg-clkc.h>

drivers/clk/meson/clk-pll.c

+13 −27
Original line number Diff line number Diff line
@@ -11,15 +11,19 @@ 
 * In the most basic form, a Meson PLL is composed as follows:

 *

 *                     PLL

 *      +------------------------------+

 *        +--------------------------------+

 *        |                                |

 * in -----[ /N ]---[ *M ]---[ >>OD ]----->> out

 *      |         ^        ^           |

 *      +------------------------------+

 *        |             +--+               |

 *  in >>-----[ /N ]--->|  |      +-----+  |

 *        |             |  |------| DCO |---->> out

 *        |  +--------->|  |      +--v--+  |

 *        |  |          +--+         |     |

 *        |  |                       |     |

 *        |  +--[ *(M + (F/Fmax) ]<--+     |

 *        |                                |

 *               FREF     VCO

 *        +--------------------------------+

 *

 * out = in * (m + frac / frac_max) / (n << sum(ods))

 * out = in * (m + frac / frac_max) / n

 */



#include <linux/clk-provider.h>
@@ -46,7 +50,6 @@ static unsigned long __pll_params_to_rate(unsigned long parent_rate, 
					  struct meson_clk_pll_data *pll)

{

	u64 rate = (u64)parent_rate * pllt->m;

	unsigned int od = pllt->od + pllt->od2 + pllt->od3;



	if (frac && MESON_PARM_APPLICABLE(&pll->frac)) {

		u64 frac_rate = (u64)parent_rate * frac;
@@ -55,7 +58,7 @@ static unsigned long __pll_params_to_rate(unsigned long parent_rate, 
					 (1 << pll->frac.width));

	}



	return DIV_ROUND_UP_ULL(rate, pllt->n << od);

	return DIV_ROUND_UP_ULL(rate, pllt->n);

}



static unsigned long meson_clk_pll_recalc_rate(struct clk_hw *hw,
@@ -68,15 +71,6 @@ static unsigned long meson_clk_pll_recalc_rate(struct clk_hw *hw, 


	pllt.n = meson_parm_read(clk->map, &pll->n);

	pllt.m = meson_parm_read(clk->map, &pll->m);

	pllt.od = meson_parm_read(clk->map, &pll->od);



	pllt.od2 = MESON_PARM_APPLICABLE(&pll->od2) ?

		meson_parm_read(clk->map, &pll->od2) :

		0;



	pllt.od3 = MESON_PARM_APPLICABLE(&pll->od3) ?

		meson_parm_read(clk->map, &pll->od3) :

		0;



	frac = MESON_PARM_APPLICABLE(&pll->frac) ?

		meson_parm_read(clk->map, &pll->frac) :
@@ -93,8 +87,6 @@ static u16 __pll_params_with_frac(unsigned long rate, 
	u16 frac_max = (1 << pll->frac.width);

	u64 val = (u64)rate * pllt->n;



	val <<= pllt->od + pllt->od2 + pllt->od3;



	if (pll->flags & CLK_MESON_PLL_ROUND_CLOSEST)

		val = DIV_ROUND_CLOSEST_ULL(val * frac_max, parent_rate);

	else
@@ -242,13 +234,7 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, 


	meson_parm_write(clk->map, &pll->n, pllt->n);

	meson_parm_write(clk->map, &pll->m, pllt->m);

	meson_parm_write(clk->map, &pll->od, pllt->od);



	if (MESON_PARM_APPLICABLE(&pll->od2))

		meson_parm_write(clk->map, &pll->od2, pllt->od2);



	if (MESON_PARM_APPLICABLE(&pll->od3))

		meson_parm_write(clk->map, &pll->od3, pllt->od3);



	if (MESON_PARM_APPLICABLE(&pll->frac)) {

		frac = __pll_params_with_frac(rate, parent_rate, pllt, pll);

drivers/clk/meson/clkc.h

+1 −8
Original line number Diff line number Diff line
@@ -47,17 +47,13 @@ struct pll_rate_table { 
	unsigned long	rate;

	u16		m;

	u16		n;

	u16		od;

	u16		od2;

	u16		od3;

};



#define PLL_RATE(_r, _m, _n, _od)					\

#define PLL_RATE(_r, _m, _n)						\

	{								\

		.rate		= (_r),					\

		.m		= (_m),					\

		.n		= (_n),					\

		.od		= (_od),				\

	}



#define CLK_MESON_PLL_ROUND_CLOSEST	BIT(0)
@@ -67,9 +63,6 @@ struct meson_clk_pll_data { 
	struct parm m;

	struct parm n;

	struct parm frac;

	struct parm od;

	struct parm od2;

	struct parm od3;

	struct parm l;

	struct parm rst;

	const struct reg_sequence *init_regs;

drivers/clk/meson/gxbb.c

+228 −256

File changed.

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