Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 8714652f authored by David S. Miller's avatar David S. Miller
Browse files

Merge tag 'linux-can-next-for-5.4-20190814' of... 

Merge tag 'linux-can-next-for-5.4-20190814' of git://git.kernel.org/pub/scm/linux/kernel/git/mkl/linux-can-next

Marc Kleine-Budde says:

====================
pull-request: can-next 2019-08-14

this is a pull request for net-next/master consisting of 41 patches.

The first two patches are for the kvaser_pciefd driver: Christer Beskow
removes unnecessary code in the kvaser_pciefd_pwm_stop() function,
YueHaibing removes the unused including of <linux/version.h>.

In the next patch YueHaibing also removes the unused including of
<linux/version.h> in the f81601 driver.

In the ti_hecc driver the next 6 patches are by me and fix checkpatch
warnings. YueHaibing's patch removes an unused variable in the
ti_hecc_mailbox_read() function.

The next 6 patches all target the xilinx_can driver. Anssi Hannula's
patch fixes a chip start failure with an invalid bus. The patch by
Venkatesh Yadav Abbarapu skips an error message in case of a deferred
probe. The 3 patches by Appana Durga Kedareswara rao fix the RX and TX
path for CAN-FD frames. Srinivas Neeli's patch fixes the bit timing
calculations for CAN-FD.

The next 12 patches are by me and several checkpatch warnings in the
af_can, raw and bcm components.

Thomas Gleixner provides a patch for the bcm, which switches the timer
to HRTIMER_MODE_SOFT and removes the hrtimer_tasklet.

Then 6 more patches by me for the gw component, which fix checkpatch
warnings, followed by 2 patches by Oliver Hartkopp to add CAN-FD
support.

The vcan driver gets 3 patches by me, fixing checkpatch warnings.

And finally a patch by Andre Hartmann to fix typos in CAN's netlink
header.
====================
parents 8d73f8f2 3ca3c4aa

drivers/net/can/kvaser_pciefd.c

+3 −8
Original line number Diff line number Diff line
@@ -7,7 +7,6 @@ 
 */



#include <linux/kernel.h>

#include <linux/version.h>

#include <linux/module.h>

#include <linux/device.h>

#include <linux/pci.h>
@@ -643,7 +642,7 @@ static int kvaser_pciefd_bus_on(struct kvaser_pciefd_can *can) 


static void kvaser_pciefd_pwm_stop(struct kvaser_pciefd_can *can)

{

	int top, trigger;

	u8 top;

	u32 pwm_ctrl;

	unsigned long irq;
@@ -651,12 +650,8 @@ static void kvaser_pciefd_pwm_stop(struct kvaser_pciefd_can *can) 
	pwm_ctrl = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_PWM_REG);

	top = (pwm_ctrl >> KVASER_PCIEFD_KCAN_PWM_TOP_SHIFT) & 0xff;



	trigger = (100 * top + 50) / 100;

	if (trigger < 0)

		trigger = 0;



	pwm_ctrl = trigger & 0xff;

	pwm_ctrl |= (top & 0xff) << KVASER_PCIEFD_KCAN_PWM_TOP_SHIFT;

	/* Set duty cycle to zero */

	pwm_ctrl |= top;

	iowrite32(pwm_ctrl, can->reg_base + KVASER_PCIEFD_KCAN_PWM_REG);

	spin_unlock_irqrestore(&can->lock, irq);

}

drivers/net/can/sja1000/f81601.c

+0 −1
Original line number Diff line number Diff line
@@ -14,7 +14,6 @@ 
#include <linux/pci.h>

#include <linux/can/dev.h>

#include <linux/io.h>

#include <linux/version.h>



#include "sja1000.h"

drivers/net/can/ti_hecc.c

+42 −43
Original line number Diff line number Diff line
@@ -46,8 +46,7 @@ MODULE_VERSION(HECC_MODULE_VERSION); 
#define HECC_MAX_MAILBOXES	32	/* hardware mailboxes - do not change */

#define MAX_TX_PRIO		0x3F	/* hardware value - do not change */



/*

 * Important Note: TX mailbox configuration

/* Important Note: TX mailbox configuration

 * TX mailboxes should be restricted to the number of SKB buffers to avoid

 * maintaining SKB buffers separately. TX mailboxes should be a power of 2

 * for the mailbox logic to work.  Top mailbox numbers are reserved for RX
@@ -272,8 +271,8 @@ static int ti_hecc_set_btc(struct ti_hecc_priv *priv) 
		if (bit_timing->brp > 4)

			can_btc |= HECC_CANBTC_SAM;

		else

			netdev_warn(priv->ndev, "WARN: Triple"

				"sampling not set due to h/w limitations");

			netdev_warn(priv->ndev,

				    "WARN: Triple sampling not set due to h/w limitations");

	}

	can_btc |= ((bit_timing->sjw - 1) & 0x3) << 8;

	can_btc |= ((bit_timing->brp - 1) & 0xFF) << 16;
@@ -309,8 +308,7 @@ static void ti_hecc_reset(struct net_device *ndev) 
	/* Set change control request and wait till enabled */

	hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_CCR);



	/*

	 * INFO: It has been observed that at times CCE bit may not be

	/* INFO: It has been observed that at times CCE bit may not be

	 * set and hw seems to be ok even if this bit is not set so

	 * timing out with a timing of 1ms to respect the specs

	 */
@@ -320,8 +318,7 @@ static void ti_hecc_reset(struct net_device *ndev) 
		udelay(10);

	}



	/*

	 * Note: On HECC, BTC can be programmed only in initialization mode, so

	/* Note: On HECC, BTC can be programmed only in initialization mode, so

	 * it is expected that the can bittiming parameters are set via ip

	 * utility before the device is opened

	 */
@@ -330,13 +327,11 @@ static void ti_hecc_reset(struct net_device *ndev) 
	/* Clear CCR (and CANMC register) and wait for CCE = 0 enable */

	hecc_write(priv, HECC_CANMC, 0);



	/*

	 * INFO: CAN net stack handles bus off and hence disabling auto-bus-on

	/* INFO: CAN net stack handles bus off and hence disabling auto-bus-on

	 * hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_ABO);

	 */



	/*

	 * INFO: It has been observed that at times CCE bit may not be

	/* INFO: It has been observed that at times CCE bit may not be

	 * set and hw seems to be ok even if this bit is not set so

	 */

	cnt = HECC_CCE_WAIT_COUNT;
@@ -369,7 +364,8 @@ static void ti_hecc_start(struct net_device *ndev) 
	/* put HECC in initialization mode and set btc */

	ti_hecc_reset(ndev);



	priv->tx_head = priv->tx_tail = HECC_TX_MASK;

	priv->tx_head = HECC_TX_MASK;

	priv->tx_tail = HECC_TX_MASK;



	/* Enable local and global acceptance mask registers */

	hecc_write(priv, HECC_CANGAM, HECC_SET_REG);
@@ -439,8 +435,7 @@ static int ti_hecc_get_berr_counter(const struct net_device *ndev, 
	return 0;

}



/*

 * ti_hecc_xmit: HECC Transmit

/* ti_hecc_xmit: HECC Transmit

 *

 * The transmit mailboxes start from 0 to HECC_MAX_TX_MBOX. In HECC the

 * priority of the mailbox for tranmission is dependent upon priority setting
@@ -520,7 +515,8 @@ static netdev_tx_t ti_hecc_xmit(struct sk_buff *skb, struct net_device *ndev) 
	return NETDEV_TX_OK;

}



static inline struct ti_hecc_priv *rx_offload_to_priv(struct can_rx_offload *offload)

static inline

struct ti_hecc_priv *rx_offload_to_priv(struct can_rx_offload *offload)

{

	return container_of(offload, struct ti_hecc_priv, offload);

}
@@ -530,18 +526,19 @@ static unsigned int ti_hecc_mailbox_read(struct can_rx_offload *offload, 
					 u32 *timestamp, unsigned int mbxno)

{

	struct ti_hecc_priv *priv = rx_offload_to_priv(offload);

	u32 data, mbx_mask;

	u32 data;



	mbx_mask = BIT(mbxno);

	data = hecc_read_mbx(priv, mbxno, HECC_CANMID);

	if (data & HECC_CANMID_IDE)

		cf->can_id = (data & CAN_EFF_MASK) | CAN_EFF_FLAG;

	else

		cf->can_id = (data >> 18) & CAN_SFF_MASK;



	data = hecc_read_mbx(priv, mbxno, HECC_CANMCF);

	if (data & HECC_CANMCF_RTR)

		cf->can_id |= CAN_RTR_FLAG;

	cf->can_dlc = get_can_dlc(data & 0xF);



	data = hecc_read_mbx(priv, mbxno, HECC_CANMDL);

	*(__be32 *)(cf->data) = cpu_to_be32(data);

	if (cf->can_dlc > 4) {
@@ -567,7 +564,8 @@ static int ti_hecc_error(struct net_device *ndev, int int_status, 
	if (!skb) {

		if (printk_ratelimit())

			netdev_err(priv->ndev,

				"ti_hecc_error: alloc_can_err_skb() failed\n");

				   "%s: alloc_can_err_skb() failed\n",

				   __func__);

		return -ENOMEM;

	}
@@ -601,8 +599,7 @@ static int ti_hecc_error(struct net_device *ndev, int int_status, 
		hecc_clear_bit(priv, HECC_CANMC, HECC_CANMC_CCR);

	}



	/*

	 * Need to check busoff condition in error status register too to

	/* Need to check busoff condition in error status register too to

	 * ensure warning interrupts don't hog the system

	 */

	if ((int_status & HECC_CANGIF_BOIF) || (err_status & HECC_CANES_BO)) {
@@ -656,7 +653,8 @@ static irqreturn_t ti_hecc_interrupt(int irq, void *dev_id) 
	unsigned long flags, rx_pending;



	int_status = hecc_read(priv,

		(priv->use_hecc1int) ? HECC_CANGIF1 : HECC_CANGIF0);

			       priv->use_hecc1int ?

			       HECC_CANGIF1 : HECC_CANGIF0);



	if (!int_status)

		return IRQ_NONE;
@@ -678,7 +676,8 @@ static irqreturn_t ti_hecc_interrupt(int irq, void *dev_id) 
			hecc_clear_bit(priv, HECC_CANME, mbx_mask);

			spin_unlock_irqrestore(&priv->mbx_lock, flags);

			stamp = hecc_read_stamp(priv, mbxno);

			stats->tx_bytes += can_rx_offload_get_echo_skb(&priv->offload,

			stats->tx_bytes +=

				can_rx_offload_get_echo_skb(&priv->offload,

							    mbxno, stamp);

			stats->tx_packets++;

			can_led_event(ndev, CAN_LED_EVENT_TX);
@@ -686,7 +685,7 @@ static irqreturn_t ti_hecc_interrupt(int irq, void *dev_id) 
		}



		/* restart queue if wrap-up or if queue stalled on last pkt */

		if (((priv->tx_head == priv->tx_tail) &&

		if ((priv->tx_head == priv->tx_tail &&

		     ((priv->tx_head & HECC_TX_MASK) != HECC_TX_MASK)) ||

		    (((priv->tx_tail & HECC_TX_MASK) == HECC_TX_MASK) &&

		     ((priv->tx_head & HECC_TX_MASK) == HECC_TX_MASK)))

drivers/net/can/vcan.c

+7 −12
Original line number Diff line number Diff line 
/*

 * vcan.c - Virtual CAN interface

/* vcan.c - Virtual CAN interface

 *

 * Copyright (c) 2002-2017 Volkswagen Group Electronic Research

 * All rights reserved.
@@ -39,6 +38,8 @@ 
 *

 */



#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt



#include <linux/module.h>

#include <linux/init.h>

#include <linux/netdevice.h>
@@ -57,9 +58,7 @@ MODULE_LICENSE("Dual BSD/GPL"); 
MODULE_AUTHOR("Urs Thuermann <urs.thuermann@volkswagen.de>");

MODULE_ALIAS_RTNL_LINK(DRV_NAME);





/*

 * CAN test feature:

/* CAN test feature:

 * Enable the echo on driver level for testing the CAN core echo modes.

 * See Documentation/networking/can.rst for details.

 */
@@ -68,7 +67,6 @@ static bool echo; /* echo testing. Default: 0 (Off) */ 
module_param(echo, bool, 0444);

MODULE_PARM_DESC(echo, "Echo sent frames (for testing). Default: 0 (Off)");





static void vcan_rx(struct sk_buff *skb, struct net_device *dev)

{

	struct canfd_frame *cfd = (struct canfd_frame *)skb->data;
@@ -101,10 +99,8 @@ static netdev_tx_t vcan_tx(struct sk_buff *skb, struct net_device *dev) 


	if (!echo) {

		/* no echo handling available inside this driver */



		if (loop) {

			/*

			 * only count the packets here, because the

			/* only count the packets here, because the

			 * CAN core already did the echo for us

			 */

			stats->rx_packets++;
@@ -117,7 +113,6 @@ static netdev_tx_t vcan_tx(struct sk_buff *skb, struct net_device *dev) 
	/* perform standard echo handling for CAN network interfaces */



	if (loop) {



		skb = can_create_echo_skb(skb);

		if (!skb)

			return NETDEV_TX_OK;
@@ -173,10 +168,10 @@ static struct rtnl_link_ops vcan_link_ops __read_mostly = { 


static __init int vcan_init_module(void)

{

	pr_info("vcan: Virtual CAN interface driver\n");

	pr_info("Virtual CAN interface driver\n");



	if (echo)

		printk(KERN_INFO "vcan: enabled echo on driver level.\n");

		pr_info("enabled echo on driver level.\n");



	return rtnl_link_register(&vcan_link_ops);

}

drivers/net/can/xilinx_can.c

+73 −102
Original line number Diff line number Diff line
@@ -66,8 +66,7 @@ enum xcan_reg { 
#define XCAN_FRAME_DLC_OFFSET(frame_base)	((frame_base) + 0x04)

#define XCAN_FRAME_DW1_OFFSET(frame_base)	((frame_base) + 0x08)

#define XCAN_FRAME_DW2_OFFSET(frame_base)	((frame_base) + 0x0C)

#define XCANFD_FRAME_DW_OFFSET(frame_base, n)	(((frame_base) + 0x08) + \

						 ((n) * XCAN_CANFD_FRAME_SIZE))

#define XCANFD_FRAME_DW_OFFSET(frame_base)	((frame_base) + 0x08)



#define XCAN_CANFD_FRAME_SIZE		0x48

#define XCAN_TXMSG_FRAME_OFFSET(n)	(XCAN_TXMSG_BASE_OFFSET + \
@@ -124,8 +123,10 @@ enum xcan_reg { 
#define XCAN_IDR_RTR_MASK		0x00000001 /* Remote TX request */

#define XCAN_DLCR_DLC_MASK		0xF0000000 /* Data length code */

#define XCAN_FSR_FL_MASK		0x00003F00 /* RX Fill Level */

#define XCAN_2_FSR_FL_MASK		0x00007F00 /* RX Fill Level */

#define XCAN_FSR_IRI_MASK		0x00000080 /* RX Increment Read Index */

#define XCAN_FSR_RI_MASK		0x0000001F /* RX Read Index */

#define XCAN_2_FSR_RI_MASK		0x0000003F /* RX Read Index */

#define XCAN_DLCR_EDL_MASK		0x08000000 /* EDL Mask in DLC */

#define XCAN_DLCR_BRS_MASK		0x04000000 /* BRS Mask in DLC */
@@ -424,7 +425,7 @@ static int xcan_set_bittiming(struct net_device *ndev) 
		btr0 = dbt->brp - 1;



		/* Setting Time Segment 1 in BTR Register */

		btr1 = dbt->prop_seg + bt->phase_seg1 - 1;

		btr1 = dbt->prop_seg + dbt->phase_seg1 - 1;



		/* Setting Time Segment 2 in BTR Register */

		btr1 |= (dbt->phase_seg2 - 1) << priv->devtype.btr_ts2_shift;
@@ -456,9 +457,8 @@ static int xcan_set_bittiming(struct net_device *ndev) 
static int xcan_chip_start(struct net_device *ndev)

{

	struct xcan_priv *priv = netdev_priv(ndev);

	u32 reg_msr, reg_sr_mask;

	u32 reg_msr;

	int err;

	unsigned long timeout;

	u32 ier;



	/* Check if it is in reset mode */
@@ -484,10 +484,8 @@ static int xcan_chip_start(struct net_device *ndev) 
	/* Check whether it is loopback mode or normal mode  */

	if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {

		reg_msr = XCAN_MSR_LBACK_MASK;

		reg_sr_mask = XCAN_SR_LBACK_MASK;

	} else {

		reg_msr = 0x0;

		reg_sr_mask = XCAN_SR_NORMAL_MASK;

	}



	/* enable the first extended filter, if any, as cores with extended
@@ -499,14 +497,6 @@ static int xcan_chip_start(struct net_device *ndev) 
	priv->write_reg(priv, XCAN_MSR_OFFSET, reg_msr);

	priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_CEN_MASK);



	timeout = jiffies + XCAN_TIMEOUT;

	while (!(priv->read_reg(priv, XCAN_SR_OFFSET) & reg_sr_mask)) {

		if (time_after(jiffies, timeout)) {

			netdev_warn(ndev,

				    "timed out for correct mode\n");

			return -ETIMEDOUT;

		}

	}

	netdev_dbg(ndev, "status:#x%08x\n",

		   priv->read_reg(priv, XCAN_SR_OFFSET));
@@ -600,7 +590,7 @@ static void xcan_write_frame(struct xcan_priv *priv, struct sk_buff *skb, 
	if (priv->devtype.cantype == XAXI_CANFD ||

	    priv->devtype.cantype == XAXI_CANFD_2_0) {

		for (i = 0; i < cf->len; i += 4) {

			ramoff = XCANFD_FRAME_DW_OFFSET(frame_offset, dwindex) +

			ramoff = XCANFD_FRAME_DW_OFFSET(frame_offset) +

					(dwindex * XCANFD_DW_BYTES);

			priv->write_reg(priv, ramoff,

					be32_to_cpup((__be32 *)(cf->data + i)));
@@ -816,13 +806,9 @@ static int xcanfd_rx(struct net_device *ndev, int frame_base) 
	struct net_device_stats *stats = &ndev->stats;

	struct canfd_frame *cf;

	struct sk_buff *skb;

	u32 id_xcan, dlc, data[2] = {0, 0}, dwindex = 0, i, fsr, readindex;

	u32 id_xcan, dlc, data[2] = {0, 0}, dwindex = 0, i, dw_offset;



	fsr = priv->read_reg(priv, XCAN_FSR_OFFSET);

	if (fsr & XCAN_FSR_FL_MASK) {

		readindex = fsr & XCAN_FSR_RI_MASK;

		id_xcan = priv->read_reg(priv,

					 XCAN_FRAME_ID_OFFSET(frame_base));

	id_xcan = priv->read_reg(priv, XCAN_FRAME_ID_OFFSET(frame_base));

	dlc = priv->read_reg(priv, XCAN_FRAME_DLC_OFFSET(frame_base));

	if (dlc & XCAN_DLCR_EDL_MASK)

		skb = alloc_canfd_skb(ndev, &cf);
@@ -865,46 +851,25 @@ static int xcanfd_rx(struct net_device *ndev, int frame_base) 
	/* Check the frame received is FD or not*/

	if (dlc & XCAN_DLCR_EDL_MASK) {

		for (i = 0; i < cf->len; i += 4) {

				if (priv->devtype.flags & XCAN_FLAG_CANFD_2)

					data[0] = priv->read_reg(priv,

					(XCAN_RXMSG_2_FRAME_OFFSET(readindex) +

					(dwindex * XCANFD_DW_BYTES)));

				else

					data[0] = priv->read_reg(priv,

					(XCAN_RXMSG_FRAME_OFFSET(readindex) +

						(dwindex * XCANFD_DW_BYTES)));

				*(__be32 *)(cf->data + i) =

						cpu_to_be32(data[0]);

			dw_offset = XCANFD_FRAME_DW_OFFSET(frame_base) +

					(dwindex * XCANFD_DW_BYTES);

			data[0] = priv->read_reg(priv, dw_offset);

			*(__be32 *)(cf->data + i) = cpu_to_be32(data[0]);

			dwindex++;

		}

	} else {

		for (i = 0; i < cf->len; i += 4) {

				if (priv->devtype.flags & XCAN_FLAG_CANFD_2)

					data[0] = priv->read_reg(priv,

						XCAN_RXMSG_2_FRAME_OFFSET(readindex) + i);

				else

					data[0] = priv->read_reg(priv,

						XCAN_RXMSG_FRAME_OFFSET(readindex) + i);

				*(__be32 *)(cf->data + i) =

						cpu_to_be32(data[0]);

			dw_offset = XCANFD_FRAME_DW_OFFSET(frame_base);

			data[0] = priv->read_reg(priv, dw_offset + i);

			*(__be32 *)(cf->data + i) = cpu_to_be32(data[0]);

		}

	}

		/* Update FSR Register so that next packet will save to

		 * buffer

		 */

		fsr = priv->read_reg(priv, XCAN_FSR_OFFSET);

		fsr |= XCAN_FSR_IRI_MASK;

		priv->write_reg(priv, XCAN_FSR_OFFSET, fsr);

		fsr = priv->read_reg(priv, XCAN_FSR_OFFSET);

	stats->rx_bytes += cf->len;

	stats->rx_packets++;

	netif_receive_skb(skb);



	return 1;

}

	/* If FSR Register is not updated with fill level */

	return 0;

}



/**

 * xcan_current_error_state - Get current error state from HW
@@ -1164,7 +1129,7 @@ static int xcan_rx_fifo_get_next_frame(struct xcan_priv *priv) 
	int offset;



	if (priv->devtype.flags & XCAN_FLAG_RX_FIFO_MULTI) {

		u32 fsr;

		u32 fsr, mask;



		/* clear RXOK before the is-empty check so that any newly

		 * received frame will reassert it without a race
@@ -1174,12 +1139,17 @@ static int xcan_rx_fifo_get_next_frame(struct xcan_priv *priv) 
		fsr = priv->read_reg(priv, XCAN_FSR_OFFSET);



		/* check if RX FIFO is empty */

		if (!(fsr & XCAN_FSR_FL_MASK))

		if (priv->devtype.flags & XCAN_FLAG_CANFD_2)

			mask = XCAN_2_FSR_FL_MASK;

		else

			mask = XCAN_FSR_FL_MASK;



		if (!(fsr & mask))

			return -ENOENT;



		if (priv->devtype.flags & XCAN_FLAG_CANFD_2)

			offset =

			  XCAN_RXMSG_2_FRAME_OFFSET(fsr & XCAN_FSR_RI_MASK);

			  XCAN_RXMSG_2_FRAME_OFFSET(fsr & XCAN_2_FSR_RI_MASK);

		else

			offset =

			  XCAN_RXMSG_FRAME_OFFSET(fsr & XCAN_FSR_RI_MASK);
@@ -1791,6 +1761,7 @@ static int xcan_probe(struct platform_device *pdev) 
	/* Getting the CAN can_clk info */

	priv->can_clk = devm_clk_get(&pdev->dev, "can_clk");

	if (IS_ERR(priv->can_clk)) {

		if (PTR_ERR(priv->can_clk) != -EPROBE_DEFER)

			dev_err(&pdev->dev, "Device clock not found.\n");

		ret = PTR_ERR(priv->can_clk);

		goto err_free;