Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 86e9c9bf authored by Santoshkumar Zalake's avatar Santoshkumar Zalake Committed by Gerrit - the friendly Code Review server
Browse files

ARM: dts: msm: enable SiRF GNSS Driver and hsuart1 

DTS Entries to enable SiRF GNSS Driver and hsuart1 serial port
for sa8155au.

Change-Id: Ia7496d4201f1aa9cf53ca96cf71b23c16a68be6c
parent 71b985ba

qcom/sa8155-adp-common.dtsi

+12 −0
Original line number Diff line number Diff line
@@ -72,6 +72,10 @@ 
	status = "ok";

};



&qupv3_se4_2uart {

	status = "ok";

};



&qupv3_se12_2uart {

	status = "ok";

};
@@ -86,6 +90,14 @@ 
		qcom,pil-force-shutdown;

	};



	ss5_pwr_ctrl0 {

		compatible = "gnss_sirf";

		pinctrl-0 = <&ss5_pwr_ctrl_rst_on>;

		ssVreset-gpio = <&tlmm 11 1>;

		ssVonoff-gpio = <&tlmm 39 1>;

		ssVboot-gpio = <&tlmm 40 1>;

	};



	qcom,turing@8300000 {

		status = "ok";

	};

qcom/sm8150-pinctrl.dtsi

+23 −11
Original line number Diff line number Diff line
@@ -723,7 +723,6 @@ 
					bias-disable;

				};

			};



			qupv3_se3_spi_miso_sleep: qupv3_se3_spi_miso_sleep {

				mux {

					pins = "gpio144";
@@ -741,13 +740,13 @@ 
		ss5_pwr_ctrl_pins: ss5_pwr_ctrl_pins {

			ss5_pwr_ctrl_rst_on: ss5_pwr_ctrl_rst_on {

				mux {

					pins = "gpio11", "gpio39";

					pins = "gpio11", "gpio39", "gpio40";

					function = "gpio";

				};



				config {

					pins = "gpio11", "gpio39";

					drive-strength = <16>; /* 16 mA */

					pins = "gpio11", "gpio39", "gpio40";

					drive-strength = <2>; /* 2 mA */

					bias-pull-up;

					output-high;

				};
@@ -755,15 +754,15 @@ 


			ss5_pwr_ctrl_rst_off: ss5_pwr_ctrl_off {

				mux {

					pins = "gpio11", "gpio39";

					pins = "gpio11", "gpio39", "gpio40";

					function = "gpio";

				};



				config {

					pins = "gpio11", "gpio39";

					drive-strength = <16>; /* 16 mA */

					bias-pull-up;

					output-high;

					pins = "gpio11", "gpio39", "gpio40";

					drive-strength = <2>; /* 2 mA */

					bias-pull-down;

					output-low;

				};

			};

		};
@@ -830,6 +829,19 @@ 
		};



		qupv3_se4_2uart_pins: qupv3_se4_2uart_pins {

			qupv3_se4_2uart_default: qupv3_se4_2uart_default {

				mux {

					pins = "gpio41", "gpio42";

					function = "gpio";

				};



				config {

					pins = "gpio41", "gpio42";

					drive-strength = <2>;

					bias-disable;

				};

			};



			qupv3_se4_2uart_active: qupv3_se4_2uart_active {

				mux {

					pins = "gpio41", "gpio42";
@@ -838,7 +850,7 @@ 


				config {

					pins = "gpio41", "gpio42";

					drive-strength = <16>;

					drive-strength = <2>;

					bias-disable;

				};

			};
@@ -851,7 +863,7 @@ 


				config {

					pins = "gpio41", "gpio42";

					drive-strength = <16>;

					drive-strength = <2>;

					bias-disable;

				};

			};

qcom/sm8150-qupv3.dtsi

+19 −1
Original line number Diff line number Diff line
@@ -336,10 +336,28 @@ 
			<MASTER_QUP_1 SLAVE_EBI1>;

		iommus = <&apps_smmu 0x603 0x0>;

		qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;

		qcom,iommu-dma = "fastmap";

		qcom,iommu-dma = "bypass";

		status = "ok";

	};



	/* GNSS UART Instance for CDP/MTP platform */

	qupv3_se4_2uart: qcom,qup_uart@a84000 {

		compatible = "qcom,msm-geni-serial-hs";

		reg = <0xa84000 0x4000>;

		reg-names = "se_phys";

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>,

			<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,

			<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;

		pinctrl-names = "default","active", "sleep";

		pinctrl-0 = <&qupv3_se4_2uart_default>;

		pinctrl-1 = <&qupv3_se4_2uart_active>;

		pinctrl-2 = <&qupv3_se4_2uart_sleep>;

		interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;

		qcom,wrapper-core = <&qupv3_1>;

		status = "disabled";

	};



	/* Debug UART Instance for CDP/MTP platform */

	qupv3_se12_2uart: qcom,qup_uart@0xa90000 {

		compatible = "qcom,msm-geni-console";

qcom/sm8150.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -40,6 +40,7 @@ 
		pci-domain1 = &pcie1; /* PCIe1 domain */

		serial0 = &qupv3_se12_2uart;

		hsuart0 = &qupv3_se13_4uart;

		hsuart1 = &qupv3_se4_2uart;

		spi22 = &qupv3_se22_spi;

	};