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Commit 8693607a authored by Ben Widawsky's avatar Ben Widawsky Committed by Daniel Vetter
Browse files

drm/i915: No LLC_MLC for HSW. 



The mid-level cache or as it's more commonly referred to now as L3, is
not setup this way on HSW.

Signed-off-by: default avatarBen Widawsky <ben@bwidawsk.net>
Reviewed-by: default avatarMika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 17f10fdc

drivers/gpu/drm/i915/i915_gem_gtt.c

+7 −3
Original line number Diff line number Diff line
@@ -217,6 +217,10 @@ void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, 


	switch (cache_level) {

	case I915_CACHE_LLC_MLC:

		/* Haswell doesn't set L3 this way */

		if (IS_HASWELL(obj->base.dev))

			pte_flags |= GEN6_PTE_CACHE_LLC;

		else

			pte_flags |= GEN6_PTE_CACHE_LLC_MLC;

		break;

	case I915_CACHE_LLC:
@@ -252,12 +256,12 @@ static unsigned int cache_level_to_agp_type(struct drm_device *dev, 
{

	switch (cache_level) {

	case I915_CACHE_LLC_MLC:

		if (INTEL_INFO(dev)->gen >= 6)

			return AGP_USER_CACHED_MEMORY_LLC_MLC;

		/* Older chipsets do not have this extra level of CPU

		 * cacheing, so fallthrough and request the PTE simply

		 * as cached.

		 */

		if (INTEL_INFO(dev)->gen >= 6 && !IS_HASWELL(dev))

			return AGP_USER_CACHED_MEMORY_LLC_MLC;

	case I915_CACHE_LLC:

		return AGP_USER_CACHED_MEMORY;

	default: